80cb9aee01
Adding a Host Mode USB driver for the Freescale 83xx. This driver supports both the Dual-Role (DR) controller and the Multi-Port-Host (MPH) controller present in the Freescale MPC8349. It has been tested with the MPC8349CDS reference system. This driver depends on platform support code for setting up the pins on the device package in a manner appropriate for the board in use. Note that this patch requires selecting the EHCI controller option under the USB Host menu. Signed-off-by: Randy Vinson <rvinson@mvista.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
38 lines
1.5 KiB
C
38 lines
1.5 KiB
C
/* Copyright (c) 2005 freescale semiconductor
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* Copyright (c) 2005 MontaVista Software
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _EHCI_FSL_H
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#define _EHCI_FSL_H
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/* offsets for the non-ehci registers in the FSL SOC USB controller */
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#define FSL_SOC_USB_ULPIVP 0x170
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#define FSL_SOC_USB_PORTSC1 0x184
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#define PORT_PTS_MSK (3<<30)
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#define PORT_PTS_UTMI (0<<30)
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#define PORT_PTS_ULPI (2<<30)
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#define PORT_PTS_SERIAL (3<<30)
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#define PORT_PTS_PTW (1<<28)
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#define FSL_SOC_USB_PORTSC2 0x188
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#define FSL_SOC_USB_USBMODE 0x1a8
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#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
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#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
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#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
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#define FSL_SOC_USB_SICTRL 0x40c /* NOTE: big-endian */
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#define FSL_SOC_USB_PRICTRL 0x410 /* NOTE: big-endian */
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#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
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#endif /* _EHCI_FSL_H */
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