5f7f6a4a0d
This patch adds support for Samsung S5P6442 CPU. This patch also adds an entry for S5P6442 cpu in plat-s5p cpu table. Signed-off-by: Adityapratap Sharma <aditya.ps@samsung.com> Signed-off-by: Atul Dahiya <atul.dahiya@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
124 lines
4.9 KiB
C
124 lines
4.9 KiB
C
/* linux/arch/arm/mach-s5p6442/include/mach/gpio.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P6442 - GPIO lib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_GPIO_H
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#define __ASM_ARCH_GPIO_H __FILE__
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#define gpio_get_value __gpio_get_value
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#define gpio_set_value __gpio_set_value
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#define gpio_cansleep __gpio_cansleep
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#define gpio_to_irq __gpio_to_irq
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/* GPIO bank sizes */
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#define S5P6442_GPIO_A0_NR (8)
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#define S5P6442_GPIO_A1_NR (2)
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#define S5P6442_GPIO_B_NR (4)
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#define S5P6442_GPIO_C0_NR (5)
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#define S5P6442_GPIO_C1_NR (5)
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#define S5P6442_GPIO_D0_NR (2)
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#define S5P6442_GPIO_D1_NR (6)
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#define S5P6442_GPIO_E0_NR (8)
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#define S5P6442_GPIO_E1_NR (5)
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#define S5P6442_GPIO_F0_NR (8)
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#define S5P6442_GPIO_F1_NR (8)
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#define S5P6442_GPIO_F2_NR (8)
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#define S5P6442_GPIO_F3_NR (6)
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#define S5P6442_GPIO_G0_NR (7)
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#define S5P6442_GPIO_G1_NR (7)
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#define S5P6442_GPIO_G2_NR (7)
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#define S5P6442_GPIO_H0_NR (8)
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#define S5P6442_GPIO_H1_NR (8)
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#define S5P6442_GPIO_H2_NR (8)
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#define S5P6442_GPIO_H3_NR (8)
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#define S5P6442_GPIO_J0_NR (8)
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#define S5P6442_GPIO_J1_NR (6)
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#define S5P6442_GPIO_J2_NR (8)
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#define S5P6442_GPIO_J3_NR (8)
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#define S5P6442_GPIO_J4_NR (5)
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/* GPIO bank numbers */
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/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
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* space for debugging purposes so that any accidental
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* change from one gpio bank to another can be caught.
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*/
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#define S5P6442_GPIO_NEXT(__gpio) \
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((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
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enum s5p_gpio_number {
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S5P6442_GPIO_A0_START = 0,
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S5P6442_GPIO_A1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A0),
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S5P6442_GPIO_B_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A1),
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S5P6442_GPIO_C0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_B),
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S5P6442_GPIO_C1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C0),
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S5P6442_GPIO_D0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C1),
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S5P6442_GPIO_D1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D0),
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S5P6442_GPIO_E0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D1),
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S5P6442_GPIO_E1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E0),
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S5P6442_GPIO_F0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E1),
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S5P6442_GPIO_F1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F0),
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S5P6442_GPIO_F2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F1),
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S5P6442_GPIO_F3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F2),
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S5P6442_GPIO_G0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F3),
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S5P6442_GPIO_G1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G0),
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S5P6442_GPIO_G2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G1),
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S5P6442_GPIO_H0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G2),
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S5P6442_GPIO_H1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H0),
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S5P6442_GPIO_H2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H1),
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S5P6442_GPIO_H3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H2),
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S5P6442_GPIO_J0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H3),
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S5P6442_GPIO_J1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J0),
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S5P6442_GPIO_J2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J1),
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S5P6442_GPIO_J3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J2),
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S5P6442_GPIO_J4_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J3),
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};
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/* S5P6442 GPIO number definitions. */
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#define S5P6442_GPA0(_nr) (S5P6442_GPIO_A0_START + (_nr))
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#define S5P6442_GPA1(_nr) (S5P6442_GPIO_A1_START + (_nr))
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#define S5P6442_GPB(_nr) (S5P6442_GPIO_B_START + (_nr))
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#define S5P6442_GPC0(_nr) (S5P6442_GPIO_C0_START + (_nr))
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#define S5P6442_GPC1(_nr) (S5P6442_GPIO_C1_START + (_nr))
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#define S5P6442_GPD0(_nr) (S5P6442_GPIO_D0_START + (_nr))
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#define S5P6442_GPD1(_nr) (S5P6442_GPIO_D1_START + (_nr))
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#define S5P6442_GPE0(_nr) (S5P6442_GPIO_E0_START + (_nr))
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#define S5P6442_GPE1(_nr) (S5P6442_GPIO_E1_START + (_nr))
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#define S5P6442_GPF0(_nr) (S5P6442_GPIO_F0_START + (_nr))
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#define S5P6442_GPF1(_nr) (S5P6442_GPIO_F1_START + (_nr))
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#define S5P6442_GPF2(_nr) (S5P6442_GPIO_F2_START + (_nr))
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#define S5P6442_GPF3(_nr) (S5P6442_GPIO_F3_START + (_nr))
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#define S5P6442_GPG0(_nr) (S5P6442_GPIO_G0_START + (_nr))
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#define S5P6442_GPG1(_nr) (S5P6442_GPIO_G1_START + (_nr))
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#define S5P6442_GPG2(_nr) (S5P6442_GPIO_G2_START + (_nr))
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#define S5P6442_GPH0(_nr) (S5P6442_GPIO_H0_START + (_nr))
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#define S5P6442_GPH1(_nr) (S5P6442_GPIO_H1_START + (_nr))
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#define S5P6442_GPH2(_nr) (S5P6442_GPIO_H2_START + (_nr))
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#define S5P6442_GPH3(_nr) (S5P6442_GPIO_H3_START + (_nr))
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#define S5P6442_GPJ0(_nr) (S5P6442_GPIO_J0_START + (_nr))
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#define S5P6442_GPJ1(_nr) (S5P6442_GPIO_J1_START + (_nr))
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#define S5P6442_GPJ2(_nr) (S5P6442_GPIO_J2_START + (_nr))
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#define S5P6442_GPJ3(_nr) (S5P6442_GPIO_J3_START + (_nr))
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#define S5P6442_GPJ4(_nr) (S5P6442_GPIO_J4_START + (_nr))
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/* the end of the S5P6442 specific gpios */
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#define S5P6442_GPIO_END (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + 1)
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#define S3C_GPIO_END S5P6442_GPIO_END
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/* define the number of gpios we need to the one after the GPJ4() range */
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#define ARCH_NR_GPIOS (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + \
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CONFIG_SAMSUNG_GPIO_EXTRA + 1)
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#include <asm-generic/gpio.h>
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#endif /* __ASM_ARCH_GPIO_H */
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