d96a980441
All current Simtec designs source the DCLK outputs from the UPLL. This means the DCLK's parent must be set to UPLL so that anything enabling and disabling an UPLL sourced clock does not shutdown the DCLK due to missing open counts. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
405 lines
9.3 KiB
C
405 lines
9.3 KiB
C
/* linux/arch/arm/mach-s3c2440/mach-osiris.c
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*
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* Copyright (c) 2005 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/sysdev.h>
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#include <linux/serial_core.h>
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#include <linux/clk.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/osiris-map.h>
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#include <asm/arch/osiris-cpld.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <asm/plat-s3c/regs-serial.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-mem.h>
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#include <asm/arch/regs-lcd.h>
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#include <asm/plat-s3c/nand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <asm/plat-s3c24xx/clock.h>
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#include <asm/plat-s3c24xx/devs.h>
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#include <asm/plat-s3c24xx/cpu.h>
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/* onboard perihperal map */
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static struct map_desc osiris_iodesc[] __initdata = {
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/* ISA IO areas (may be over-written later) */
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{
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.virtual = (u32)S3C24XX_VA_ISA_BYTE,
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.pfn = __phys_to_pfn(S3C2410_CS5),
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.length = SZ_16M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = __phys_to_pfn(S3C2410_CS5),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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/* CPLD control registers */
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{
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.virtual = (u32)OSIRIS_VA_CTRL0,
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.pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)OSIRIS_VA_CTRL1,
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.pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)OSIRIS_VA_CTRL2,
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.pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)OSIRIS_VA_IDREG,
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.pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
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.length = SZ_16K,
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.type = MT_DEVICE,
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},
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};
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#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
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#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
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#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
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static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
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[0] = {
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.name = "uclk",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 0,
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},
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[1] = {
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.name = "pclk",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 0,
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}
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};
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static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clocks = osiris_serial_clocks,
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.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clocks = osiris_serial_clocks,
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.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
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},
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clocks = osiris_serial_clocks,
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.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
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}
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};
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/* NAND Flash on Osiris board */
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static int external_map[] = { 2 };
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static int chip0_map[] = { 0 };
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static int chip1_map[] = { 1 };
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static struct mtd_partition osiris_default_nand_part[] = {
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[0] = {
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.name = "Boot Agent",
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.size = SZ_16K,
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.offset = 0,
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},
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[1] = {
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.name = "/boot",
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.size = SZ_4M - SZ_16K,
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.offset = SZ_16K,
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},
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[2] = {
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.name = "user1",
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.offset = SZ_4M,
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.size = SZ_32M - SZ_4M,
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},
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[3] = {
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.name = "user2",
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.offset = SZ_32M,
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.size = MTDPART_SIZ_FULL,
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}
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};
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static struct mtd_partition osiris_default_nand_part_large[] = {
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[0] = {
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.name = "Boot Agent",
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.size = SZ_128K,
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.offset = 0,
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},
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[1] = {
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.name = "/boot",
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.size = SZ_4M - SZ_128K,
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.offset = SZ_128K,
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},
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[2] = {
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.name = "user1",
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.offset = SZ_4M,
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.size = SZ_32M - SZ_4M,
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},
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[3] = {
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.name = "user2",
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.offset = SZ_32M,
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.size = MTDPART_SIZ_FULL,
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}
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};
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/* the Osiris has 3 selectable slots for nand-flash, the two
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* on-board chip areas, as well as the external slot.
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*
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* Note, there is no current hot-plug support for the External
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* socket.
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*/
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static struct s3c2410_nand_set osiris_nand_sets[] = {
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[1] = {
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.name = "External",
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.nr_chips = 1,
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.nr_map = external_map,
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.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
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.partitions = osiris_default_nand_part,
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},
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[0] = {
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.name = "chip0",
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.nr_chips = 1,
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.nr_map = chip0_map,
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.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
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.partitions = osiris_default_nand_part,
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},
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[2] = {
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.name = "chip1",
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.nr_chips = 1,
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.nr_map = chip1_map,
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.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
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.partitions = osiris_default_nand_part,
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},
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};
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static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
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{
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unsigned int tmp;
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slot = set->nr_map[slot] & 3;
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pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
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slot, set, set->nr_map);
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tmp = __raw_readb(OSIRIS_VA_CTRL0);
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tmp &= ~OSIRIS_CTRL0_NANDSEL;
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tmp |= slot;
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pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
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__raw_writeb(tmp, OSIRIS_VA_CTRL0);
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}
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static struct s3c2410_platform_nand osiris_nand_info = {
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.tacls = 25,
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.twrph0 = 60,
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.twrph1 = 60,
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.nr_sets = ARRAY_SIZE(osiris_nand_sets),
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.sets = osiris_nand_sets,
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.select_chip = osiris_nand_select,
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};
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/* PCMCIA control and configuration */
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static struct resource osiris_pcmcia_resource[] = {
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[0] = {
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.start = 0x0f000000,
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.end = 0x0f100000,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 0x0c000000,
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.end = 0x0c100000,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct platform_device osiris_pcmcia = {
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.name = "osiris-pcmcia",
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.id = -1,
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.num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
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.resource = osiris_pcmcia_resource,
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};
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/* Osiris power management device */
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#ifdef CONFIG_PM
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static unsigned char pm_osiris_ctrl0;
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static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
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{
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unsigned int tmp;
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pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
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tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
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/* ensure correct NAND slot is selected on resume */
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if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
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tmp |= 2;
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__raw_writeb(tmp, OSIRIS_VA_CTRL0);
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/* ensure that an nRESET is not generated on resume. */
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s3c2410_gpio_setpin(S3C2410_GPA21, 1);
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s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
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return 0;
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}
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static int osiris_pm_resume(struct sys_device *sd)
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{
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if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
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__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
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__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
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s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
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return 0;
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}
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#else
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#define osiris_pm_suspend NULL
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#define osiris_pm_resume NULL
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#endif
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static struct sysdev_class osiris_pm_sysclass = {
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.name = "mach-osiris",
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.suspend = osiris_pm_suspend,
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.resume = osiris_pm_resume,
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};
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static struct sys_device osiris_pm_sysdev = {
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.cls = &osiris_pm_sysclass,
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};
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/* Standard Osiris devices */
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static struct platform_device *osiris_devices[] __initdata = {
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&s3c_device_i2c,
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&s3c_device_wdt,
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&s3c_device_nand,
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&osiris_pcmcia,
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};
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static struct clk *osiris_clocks[] = {
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&s3c24xx_dclk0,
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&s3c24xx_dclk1,
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&s3c24xx_clkout0,
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&s3c24xx_clkout1,
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&s3c24xx_uclk,
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};
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static void __init osiris_map_io(void)
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{
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unsigned long flags;
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/* initialise the clocks */
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s3c24xx_dclk0.parent = &clk_upll;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk1.parent = &clk_upll;
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s3c24xx_dclk1.rate = 24*1000*1000;
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s3c24xx_clkout0.parent = &s3c24xx_dclk0;
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s3c24xx_clkout1.parent = &s3c24xx_dclk1;
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s3c24xx_uclk.parent = &s3c24xx_clkout1;
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s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
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s3c_device_nand.dev.platform_data = &osiris_nand_info;
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s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
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s3c24xx_init_clocks(0);
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s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
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/* check for the newer revision boards with large page nand */
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if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
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printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
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__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
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osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
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osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
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} else {
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/* write-protect line to the NAND */
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s3c2410_gpio_setpin(S3C2410_GPA0, 1);
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}
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/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
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local_irq_save(flags);
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__raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
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local_irq_restore(flags);
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}
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static void __init osiris_init(void)
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{
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sysdev_class_register(&osiris_pm_sysclass);
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sysdev_register(&osiris_pm_sysdev);
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platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
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};
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MACHINE_START(OSIRIS, "Simtec-OSIRIS")
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/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
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.phys_io = S3C2410_PA_UART,
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.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
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.boot_params = S3C2410_SDRAM_PA + 0x100,
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.map_io = osiris_map_io,
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.init_machine = osiris_init,
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.init_irq = s3c24xx_init_irq,
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.init_machine = osiris_init,
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.timer = &s3c24xx_timer,
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MACHINE_END
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