679292993c
It was using an immediate _PAGE_EXEC_4U value in an 'and' instruction to perform the test. This doesn't work because the immediate field is signed 13-bit, this the mask being tested against the PTE was 0x1000 sign-extended to 32-bits instead of just plain 0x1000. Signed-off-by: David S. Miller <davem@davemloft.net>
40 lines
854 B
ArmAsm
40 lines
854 B
ArmAsm
/* ITLB ** ICACHE line 1: Context 0 check and TSB load */
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ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
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ldxa [%g0] ASI_IMMU, %g6 ! Get TAG TARGET
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srlx %g6, 48, %g5 ! Get context
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sllx %g6, 22, %g6 ! Zero out context
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brz,pn %g5, kvmap_itlb ! Context 0 processing
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srlx %g6, 22, %g6 ! Delay slot
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TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
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cmp %g4, %g6 ! Compare TAG
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/* ITLB ** ICACHE line 2: TSB compare and TLB load */
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bne,pn %xcc, tsb_miss_itlb ! Miss
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mov FAULT_CODE_ITLB, %g3
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sethi %hi(_PAGE_EXEC_4U), %g4
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andcc %g5, %g4, %g0 ! Executable?
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be,pn %xcc, tsb_do_fault
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nop ! Delay slot, fill me
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stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB
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retry ! Trap done
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/* ITLB ** ICACHE line 3: */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/* ITLB ** ICACHE line 4: */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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