d7cf0edb8f
The per-processor interrupt request register and current processor priority register are only accessed on the current cpu. In fact the hypervisor doesn't even let us choose which cpu's registers to access. The only function to use cpu twice is xics_migrate_irqs_away, not a fast path. But we can cache the result of get_hard_processor_id() instead of calling get_hard_smp_processor_id(cpu) in a loop across the call to rtas. Years ago the irq code passed smp_processor_id into get_irq, I thought we might initialize the CPPR third party at boot as an extra measure of saftey, and it made the code symmetric with the qirr (queued interrupt for software generated interrupts), but now it is just extra and sometimes unneeded work to pass it down. Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
34 lines
955 B
C
34 lines
955 B
C
/*
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* arch/powerpc/platforms/pseries/xics.h
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*
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* Copyright 2000 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _POWERPC_KERNEL_XICS_H
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#define _POWERPC_KERNEL_XICS_H
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#include <linux/cache.h>
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extern void xics_init_IRQ(void);
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extern void xics_setup_cpu(void);
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extern void xics_teardown_cpu(int secondary);
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extern void xics_cause_IPI(int cpu);
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extern void xics_request_IPIs(void);
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extern void xics_migrate_irqs_away(void);
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struct xics_ipi_struct {
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volatile unsigned long value;
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} ____cacheline_aligned;
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extern struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
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struct irq_desc;
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extern void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc);
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#endif /* _POWERPC_KERNEL_XICS_H */
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