d73d65fab1
Some of the omap2, omap3 peripherals support software reset. This can be done through the softreset bit in sysconfig register. The reset status can be checked through resetdone bit of sysstatus register. syss_has_reset_status is added to the hwmod database of peripherals which have resetdone bit in sysstatus register. Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@ti.com> Reviewed-by: Govindraj.R <govindraj.raja@ti.com> Signed-off-by: Avinash.H.M <avinashhm@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
1400 lines
36 KiB
C
1400 lines
36 KiB
C
/*
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* omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
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*
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* Copyright (C) 2009-2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The data in this file should be completely autogeneratable from
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* the TI hardware database or other technical documentation.
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*
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* XXX these should be marked initdata for multi-OMAP kernels
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*/
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#include <plat/omap_hwmod.h>
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#include <mach/irqs.h>
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#include <plat/cpu.h>
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#include <plat/dma.h>
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#include <plat/serial.h>
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#include <plat/l4_3xxx.h>
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#include <plat/i2c.h>
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#include <plat/gpio.h>
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#include <plat/smartreflex.h>
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#include "omap_hwmod_common_data.h"
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#include "prm-regbits-34xx.h"
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#include "cm-regbits-34xx.h"
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#include "wd_timer.h"
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/*
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* OMAP3xxx hardware module integration data
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*
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* ALl of the data in this section should be autogeneratable from the
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* TI hardware database or other technical documentation. Data that
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* is driver-specific or driver-kernel integration-specific belongs
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* elsewhere.
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*/
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static struct omap_hwmod omap3xxx_mpu_hwmod;
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static struct omap_hwmod omap3xxx_iva_hwmod;
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static struct omap_hwmod omap3xxx_l3_main_hwmod;
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static struct omap_hwmod omap3xxx_l4_core_hwmod;
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static struct omap_hwmod omap3xxx_l4_per_hwmod;
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static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
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static struct omap_hwmod omap3xxx_i2c1_hwmod;
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static struct omap_hwmod omap3xxx_i2c2_hwmod;
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static struct omap_hwmod omap3xxx_i2c3_hwmod;
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static struct omap_hwmod omap3xxx_gpio1_hwmod;
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static struct omap_hwmod omap3xxx_gpio2_hwmod;
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static struct omap_hwmod omap3xxx_gpio3_hwmod;
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static struct omap_hwmod omap3xxx_gpio4_hwmod;
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static struct omap_hwmod omap3xxx_gpio5_hwmod;
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static struct omap_hwmod omap3xxx_gpio6_hwmod;
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static struct omap_hwmod omap34xx_sr1_hwmod;
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static struct omap_hwmod omap34xx_sr2_hwmod;
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static struct omap_hwmod omap3xxx_dma_system_hwmod;
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/* L3 -> L4_CORE interface */
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static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
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.master = &omap3xxx_l3_main_hwmod,
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.slave = &omap3xxx_l4_core_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L3 -> L4_PER interface */
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static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
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.master = &omap3xxx_l3_main_hwmod,
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.slave = &omap3xxx_l4_per_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* MPU -> L3 interface */
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static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
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.master = &omap3xxx_mpu_hwmod,
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.slave = &omap3xxx_l3_main_hwmod,
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.user = OCP_USER_MPU,
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};
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/* Slave interfaces on the L3 interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
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&omap3xxx_mpu__l3_main,
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};
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/* Master interfaces on the L3 interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
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&omap3xxx_l3_main__l4_core,
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&omap3xxx_l3_main__l4_per,
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};
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/* L3 */
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static struct omap_hwmod omap3xxx_l3_main_hwmod = {
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.name = "l3_main",
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.class = &l3_hwmod_class,
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.masters = omap3xxx_l3_main_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
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.slaves = omap3xxx_l3_main_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.flags = HWMOD_NO_IDLEST,
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};
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static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
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static struct omap_hwmod omap3xxx_uart1_hwmod;
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static struct omap_hwmod omap3xxx_uart2_hwmod;
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static struct omap_hwmod omap3xxx_uart3_hwmod;
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static struct omap_hwmod omap3xxx_uart4_hwmod;
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/* L4_CORE -> L4_WKUP interface */
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static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_l4_wkup_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> UART1 interface */
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static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
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{
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.pa_start = OMAP3_UART1_BASE,
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.pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_uart1_hwmod,
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.clk = "uart1_ick",
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.addr = omap3xxx_uart1_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> UART2 interface */
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static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
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{
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.pa_start = OMAP3_UART2_BASE,
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.pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_uart2_hwmod,
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.clk = "uart2_ick",
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.addr = omap3xxx_uart2_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 PER -> UART3 interface */
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static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
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{
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.pa_start = OMAP3_UART3_BASE,
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.pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
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.master = &omap3xxx_l4_per_hwmod,
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.slave = &omap3xxx_uart3_hwmod,
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.clk = "uart3_ick",
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.addr = omap3xxx_uart3_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 PER -> UART4 interface */
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static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
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{
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.pa_start = OMAP3_UART4_BASE,
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.pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
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.master = &omap3xxx_l4_per_hwmod,
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.slave = &omap3xxx_uart4_hwmod,
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.clk = "uart4_ick",
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.addr = omap3xxx_uart4_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* I2C IP block address space length (in bytes) */
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#define OMAP2_I2C_AS_LEN 128
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/* L4 CORE -> I2C1 interface */
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static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
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{
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.pa_start = 0x48070000,
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.pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
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.flags = ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_i2c1_hwmod,
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.clk = "i2c1_ick",
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.addr = omap3xxx_i2c1_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
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.l4_prot_group = 7,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> I2C2 interface */
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static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
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{
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.pa_start = 0x48072000,
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.pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
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.flags = ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_i2c2_hwmod,
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.clk = "i2c2_ick",
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.addr = omap3xxx_i2c2_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
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.l4_prot_group = 7,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> I2C3 interface */
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static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
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{
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.pa_start = 0x48060000,
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.pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
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.flags = ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_i2c3_hwmod,
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.clk = "i2c3_ick",
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.addr = omap3xxx_i2c3_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
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.l4_prot_group = 7,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> SR1 interface */
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static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
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{
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.pa_start = OMAP34XX_SR1_BASE,
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.pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
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.flags = ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap34xx_sr1_hwmod,
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.clk = "sr_l4_ick",
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.addr = omap3_sr1_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
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.user = OCP_USER_MPU,
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};
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/* L4 CORE -> SR1 interface */
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static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
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{
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.pa_start = OMAP34XX_SR2_BASE,
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.pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
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.flags = ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap34xx_sr2_hwmod,
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.clk = "sr_l4_ick",
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.addr = omap3_sr2_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
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.user = OCP_USER_MPU,
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};
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/* Slave interfaces on the L4_CORE interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
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&omap3xxx_l3_main__l4_core,
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&omap3_l4_core__sr1,
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&omap3_l4_core__sr2,
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};
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/* Master interfaces on the L4_CORE interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
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&omap3xxx_l4_core__l4_wkup,
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&omap3_l4_core__uart1,
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&omap3_l4_core__uart2,
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&omap3_l4_core__i2c1,
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&omap3_l4_core__i2c2,
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&omap3_l4_core__i2c3,
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};
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/* L4 CORE */
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static struct omap_hwmod omap3xxx_l4_core_hwmod = {
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.name = "l4_core",
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.class = &l4_hwmod_class,
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.masters = omap3xxx_l4_core_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
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.slaves = omap3xxx_l4_core_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.flags = HWMOD_NO_IDLEST,
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};
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/* Slave interfaces on the L4_PER interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
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&omap3xxx_l3_main__l4_per,
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};
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/* Master interfaces on the L4_PER interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
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&omap3_l4_per__uart3,
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&omap3_l4_per__uart4,
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};
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/* L4 PER */
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static struct omap_hwmod omap3xxx_l4_per_hwmod = {
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.name = "l4_per",
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.class = &l4_hwmod_class,
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.masters = omap3xxx_l4_per_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
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.slaves = omap3xxx_l4_per_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.flags = HWMOD_NO_IDLEST,
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};
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/* Slave interfaces on the L4_WKUP interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
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&omap3xxx_l4_core__l4_wkup,
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};
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/* Master interfaces on the L4_WKUP interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
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};
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/* L4 WKUP */
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static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
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.name = "l4_wkup",
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.class = &l4_hwmod_class,
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.masters = omap3xxx_l4_wkup_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
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.slaves = omap3xxx_l4_wkup_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.flags = HWMOD_NO_IDLEST,
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};
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/* Master interfaces on the MPU device */
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static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
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&omap3xxx_mpu__l3_main,
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};
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/* MPU */
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static struct omap_hwmod omap3xxx_mpu_hwmod = {
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.name = "mpu",
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.class = &mpu_hwmod_class,
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.main_clk = "arm_fck",
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.masters = omap3xxx_mpu_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/*
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* IVA2_2 interface data
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*/
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/* IVA2 <- L3 interface */
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static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
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.master = &omap3xxx_l3_main_hwmod,
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.slave = &omap3xxx_iva_hwmod,
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.clk = "iva2_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
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&omap3xxx_l3__iva,
|
|
};
|
|
|
|
/*
|
|
* IVA2 (IVA2)
|
|
*/
|
|
|
|
static struct omap_hwmod omap3xxx_iva_hwmod = {
|
|
.name = "iva",
|
|
.class = &iva_hwmod_class,
|
|
.masters = omap3xxx_iva_masters,
|
|
.masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
|
};
|
|
|
|
/* l4_wkup -> wd_timer2 */
|
|
static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
|
|
{
|
|
.pa_start = 0x48314000,
|
|
.pa_end = 0x4831407f,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
|
|
.master = &omap3xxx_l4_wkup_hwmod,
|
|
.slave = &omap3xxx_wd_timer2_hwmod,
|
|
.clk = "wdt2_ick",
|
|
.addr = omap3xxx_wd_timer2_addrs,
|
|
.addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/*
|
|
* 'wd_timer' class
|
|
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
|
|
* overflow condition
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
/* I2C common */
|
|
static struct omap_hwmod_class_sysconfig i2c_sysc = {
|
|
.rev_offs = 0x00,
|
|
.sysc_offs = 0x20,
|
|
.syss_offs = 0x10,
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
|
|
.name = "wd_timer",
|
|
.sysc = &omap3xxx_wd_timer_sysc,
|
|
.pre_shutdown = &omap2_wd_timer_disable
|
|
};
|
|
|
|
/* wd_timer2 */
|
|
static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
|
|
&omap3xxx_l4_wkup__wd_timer2,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
|
|
.name = "wd_timer2",
|
|
.class = &omap3xxx_wd_timer_hwmod_class,
|
|
.main_clk = "wdt2_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_WDT2_SHIFT,
|
|
.module_offs = WKUP_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_wd_timer2_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* UART common */
|
|
|
|
static struct omap_hwmod_class_sysconfig uart_sysc = {
|
|
.rev_offs = 0x50,
|
|
.sysc_offs = 0x54,
|
|
.syss_offs = 0x58,
|
|
.sysc_flags = (SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class uart_class = {
|
|
.name = "uart",
|
|
.sysc = &uart_sysc,
|
|
};
|
|
|
|
/* UART1 */
|
|
|
|
static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
|
|
{ .irq = INT_24XX_UART1_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
|
|
&omap3_l4_core__uart1,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_uart1_hwmod = {
|
|
.name = "uart1",
|
|
.mpu_irqs = uart1_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
|
|
.sdma_reqs = uart1_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
|
|
.main_clk = "uart1_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_UART1_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_uart1_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
|
|
.class = &uart_class,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* UART2 */
|
|
|
|
static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
|
|
{ .irq = INT_24XX_UART2_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
|
|
&omap3_l4_core__uart2,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_uart2_hwmod = {
|
|
.name = "uart2",
|
|
.mpu_irqs = uart2_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
|
|
.sdma_reqs = uart2_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
|
|
.main_clk = "uart2_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_UART2_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_uart2_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
|
|
.class = &uart_class,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* UART3 */
|
|
|
|
static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
|
|
{ .irq = INT_24XX_UART3_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
|
|
&omap3_l4_per__uart3,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_uart3_hwmod = {
|
|
.name = "uart3",
|
|
.mpu_irqs = uart3_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
|
|
.sdma_reqs = uart3_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
|
|
.main_clk = "uart3_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = OMAP3430_PER_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_UART3_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_uart3_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
|
|
.class = &uart_class,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* UART4 */
|
|
|
|
static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
|
|
{ .irq = INT_36XX_UART4_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
|
|
{ .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
|
|
{ .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
|
|
&omap3_l4_per__uart4,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_uart4_hwmod = {
|
|
.name = "uart4",
|
|
.mpu_irqs = uart4_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
|
|
.sdma_reqs = uart4_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
|
|
.main_clk = "uart4_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = OMAP3430_PER_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3630_EN_UART4_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_uart4_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
|
|
.class = &uart_class,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
|
|
};
|
|
|
|
static struct omap_hwmod_class i2c_class = {
|
|
.name = "i2c",
|
|
.sysc = &i2c_sysc,
|
|
};
|
|
|
|
/* I2C1 */
|
|
|
|
static struct omap_i2c_dev_attr i2c1_dev_attr = {
|
|
.fifo_depth = 8, /* bytes */
|
|
};
|
|
|
|
static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
|
|
{ .irq = INT_24XX_I2C1_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
|
|
&omap3_l4_core__i2c1,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_i2c1_hwmod = {
|
|
.name = "i2c1",
|
|
.mpu_irqs = i2c1_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
|
|
.sdma_reqs = i2c1_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
|
|
.main_clk = "i2c1_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_I2C1_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_i2c1_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
|
|
.class = &i2c_class,
|
|
.dev_attr = &i2c1_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* I2C2 */
|
|
|
|
static struct omap_i2c_dev_attr i2c2_dev_attr = {
|
|
.fifo_depth = 8, /* bytes */
|
|
};
|
|
|
|
static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
|
|
{ .irq = INT_24XX_I2C2_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
|
|
&omap3_l4_core__i2c2,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_i2c2_hwmod = {
|
|
.name = "i2c2",
|
|
.mpu_irqs = i2c2_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
|
|
.sdma_reqs = i2c2_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
|
|
.main_clk = "i2c2_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_I2C2_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_i2c2_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
|
|
.class = &i2c_class,
|
|
.dev_attr = &i2c2_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* I2C3 */
|
|
|
|
static struct omap_i2c_dev_attr i2c3_dev_attr = {
|
|
.fifo_depth = 64, /* bytes */
|
|
};
|
|
|
|
static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
|
|
{ .irq = INT_34XX_I2C3_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
|
|
{ .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
|
|
&omap3_l4_core__i2c3,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_i2c3_hwmod = {
|
|
.name = "i2c3",
|
|
.mpu_irqs = i2c3_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
|
|
.sdma_reqs = i2c3_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
|
|
.main_clk = "i2c3_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_I2C3_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_i2c3_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
|
|
.class = &i2c_class,
|
|
.dev_attr = &i2c3_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* l4_wkup -> gpio1 */
|
|
static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
|
|
{
|
|
.pa_start = 0x48310000,
|
|
.pa_end = 0x483101ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
|
|
.master = &omap3xxx_l4_wkup_hwmod,
|
|
.slave = &omap3xxx_gpio1_hwmod,
|
|
.addr = omap3xxx_gpio1_addrs,
|
|
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> gpio2 */
|
|
static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
|
|
{
|
|
.pa_start = 0x49050000,
|
|
.pa_end = 0x490501ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
|
|
.master = &omap3xxx_l4_per_hwmod,
|
|
.slave = &omap3xxx_gpio2_hwmod,
|
|
.addr = omap3xxx_gpio2_addrs,
|
|
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> gpio3 */
|
|
static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
|
|
{
|
|
.pa_start = 0x49052000,
|
|
.pa_end = 0x490521ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
|
|
.master = &omap3xxx_l4_per_hwmod,
|
|
.slave = &omap3xxx_gpio3_hwmod,
|
|
.addr = omap3xxx_gpio3_addrs,
|
|
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> gpio4 */
|
|
static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
|
|
{
|
|
.pa_start = 0x49054000,
|
|
.pa_end = 0x490541ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
|
|
.master = &omap3xxx_l4_per_hwmod,
|
|
.slave = &omap3xxx_gpio4_hwmod,
|
|
.addr = omap3xxx_gpio4_addrs,
|
|
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> gpio5 */
|
|
static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
|
|
{
|
|
.pa_start = 0x49056000,
|
|
.pa_end = 0x490561ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
|
|
.master = &omap3xxx_l4_per_hwmod,
|
|
.slave = &omap3xxx_gpio5_hwmod,
|
|
.addr = omap3xxx_gpio5_addrs,
|
|
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> gpio6 */
|
|
static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
|
|
{
|
|
.pa_start = 0x49058000,
|
|
.pa_end = 0x490581ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
|
|
.master = &omap3xxx_l4_per_hwmod,
|
|
.slave = &omap3xxx_gpio6_hwmod,
|
|
.addr = omap3xxx_gpio6_addrs,
|
|
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/*
|
|
* 'gpio' class
|
|
* general purpose io module
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
|
|
.name = "gpio",
|
|
.sysc = &omap3xxx_gpio_sysc,
|
|
.rev = 1,
|
|
};
|
|
|
|
/* gpio_dev_attr*/
|
|
static struct omap_gpio_dev_attr gpio_dev_attr = {
|
|
.bank_width = 32,
|
|
.dbck_flag = true,
|
|
};
|
|
|
|
/* gpio1 */
|
|
static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
|
|
{ .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
|
|
};
|
|
|
|
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio1_dbck", },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
|
|
&omap3xxx_l4_wkup__gpio1,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_gpio1_hwmod = {
|
|
.name = "gpio1",
|
|
.mpu_irqs = omap3xxx_gpio1_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
|
|
.main_clk = "gpio1_ick",
|
|
.opt_clks = gpio1_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_GPIO1_SHIFT,
|
|
.module_offs = WKUP_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_gpio1_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
|
|
.class = &omap3xxx_gpio_hwmod_class,
|
|
.dev_attr = &gpio_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* gpio2 */
|
|
static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
|
|
{ .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
|
|
};
|
|
|
|
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio2_dbck", },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
|
|
&omap3xxx_l4_per__gpio2,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_gpio2_hwmod = {
|
|
.name = "gpio2",
|
|
.mpu_irqs = omap3xxx_gpio2_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
|
|
.main_clk = "gpio2_ick",
|
|
.opt_clks = gpio2_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_GPIO2_SHIFT,
|
|
.module_offs = OMAP3430_PER_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_gpio2_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
|
|
.class = &omap3xxx_gpio_hwmod_class,
|
|
.dev_attr = &gpio_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* gpio3 */
|
|
static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
|
|
{ .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
|
|
};
|
|
|
|
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio3_dbck", },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
|
|
&omap3xxx_l4_per__gpio3,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_gpio3_hwmod = {
|
|
.name = "gpio3",
|
|
.mpu_irqs = omap3xxx_gpio3_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
|
|
.main_clk = "gpio3_ick",
|
|
.opt_clks = gpio3_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_GPIO3_SHIFT,
|
|
.module_offs = OMAP3430_PER_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_gpio3_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
|
|
.class = &omap3xxx_gpio_hwmod_class,
|
|
.dev_attr = &gpio_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* gpio4 */
|
|
static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
|
|
{ .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
|
|
};
|
|
|
|
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio4_dbck", },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
|
|
&omap3xxx_l4_per__gpio4,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_gpio4_hwmod = {
|
|
.name = "gpio4",
|
|
.mpu_irqs = omap3xxx_gpio4_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
|
|
.main_clk = "gpio4_ick",
|
|
.opt_clks = gpio4_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_GPIO4_SHIFT,
|
|
.module_offs = OMAP3430_PER_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_gpio4_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
|
|
.class = &omap3xxx_gpio_hwmod_class,
|
|
.dev_attr = &gpio_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* gpio5 */
|
|
static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
|
|
{ .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
|
|
};
|
|
|
|
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio5_dbck", },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
|
|
&omap3xxx_l4_per__gpio5,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_gpio5_hwmod = {
|
|
.name = "gpio5",
|
|
.mpu_irqs = omap3xxx_gpio5_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
|
|
.main_clk = "gpio5_ick",
|
|
.opt_clks = gpio5_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_GPIO5_SHIFT,
|
|
.module_offs = OMAP3430_PER_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_gpio5_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
|
|
.class = &omap3xxx_gpio_hwmod_class,
|
|
.dev_attr = &gpio_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* gpio6 */
|
|
static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
|
|
{ .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
|
|
};
|
|
|
|
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio6_dbck", },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
|
|
&omap3xxx_l4_per__gpio6,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_gpio6_hwmod = {
|
|
.name = "gpio6",
|
|
.mpu_irqs = omap3xxx_gpio6_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
|
|
.main_clk = "gpio6_ick",
|
|
.opt_clks = gpio6_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_GPIO6_SHIFT,
|
|
.module_offs = OMAP3430_PER_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_gpio6_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
|
|
.class = &omap3xxx_gpio_hwmod_class,
|
|
.dev_attr = &gpio_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* dma_system -> L3 */
|
|
static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
|
|
.master = &omap3xxx_dma_system_hwmod,
|
|
.slave = &omap3xxx_l3_main_hwmod,
|
|
.clk = "core_l3_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* dma attributes */
|
|
static struct omap_dma_dev_attr dma_dev_attr = {
|
|
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
|
|
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
|
|
.lch_count = 32,
|
|
};
|
|
|
|
static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x002c,
|
|
.syss_offs = 0x0028,
|
|
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
|
|
SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
|
|
.name = "dma",
|
|
.sysc = &omap3xxx_dma_sysc,
|
|
};
|
|
|
|
/* dma_system */
|
|
static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
|
|
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
|
|
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
|
|
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
|
|
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
|
|
};
|
|
|
|
static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
|
|
{
|
|
.pa_start = 0x48056000,
|
|
.pa_end = 0x4a0560ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
/* dma_system master ports */
|
|
static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
|
|
&omap3xxx_dma_system__l3,
|
|
};
|
|
|
|
/* l4_cfg -> dma_system */
|
|
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
|
|
.master = &omap3xxx_l4_core_hwmod,
|
|
.slave = &omap3xxx_dma_system_hwmod,
|
|
.clk = "core_l4_ick",
|
|
.addr = omap3xxx_dma_system_addrs,
|
|
.addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* dma_system slave ports */
|
|
static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
|
|
&omap3xxx_l4_core__dma_system,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_dma_system_hwmod = {
|
|
.name = "dma",
|
|
.class = &omap3xxx_dma_hwmod_class,
|
|
.mpu_irqs = omap3xxx_dma_system_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
|
|
.main_clk = "core_l3_ick",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_ST_SDMA_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_dma_system_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
|
|
.masters = omap3xxx_dma_system_masters,
|
|
.masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
|
|
.dev_attr = &dma_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
.flags = HWMOD_NO_IDLEST,
|
|
};
|
|
|
|
/* SR common */
|
|
static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
|
|
.clkact_shift = 20,
|
|
};
|
|
|
|
static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
|
|
.sysc_offs = 0x24,
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
|
|
.clockact = CLOCKACT_TEST_ICLK,
|
|
.sysc_fields = &omap34xx_sr_sysc_fields,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
|
|
.name = "smartreflex",
|
|
.sysc = &omap34xx_sr_sysc,
|
|
.rev = 1,
|
|
};
|
|
|
|
static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
|
|
.sidle_shift = 24,
|
|
.enwkup_shift = 26
|
|
};
|
|
|
|
static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
|
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.sysc_offs = 0x38,
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
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SYSC_NO_CACHE),
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.sysc_fields = &omap36xx_sr_sysc_fields,
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};
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|
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static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
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.name = "smartreflex",
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.sysc = &omap36xx_sr_sysc,
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.rev = 2,
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};
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|
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/* SR1 */
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static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
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&omap3_l4_core__sr1,
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};
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static struct omap_hwmod omap34xx_sr1_hwmod = {
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.name = "sr1_hwmod",
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.class = &omap34xx_smartreflex_hwmod_class,
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.main_clk = "sr1_fck",
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.vdd_name = "mpu",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_SR1_SHIFT,
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
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},
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},
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.slaves = omap3_sr1_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
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CHIP_IS_OMAP3430ES3_0 |
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CHIP_IS_OMAP3430ES3_1),
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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|
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static struct omap_hwmod omap36xx_sr1_hwmod = {
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.name = "sr1_hwmod",
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.class = &omap36xx_smartreflex_hwmod_class,
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.main_clk = "sr1_fck",
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.vdd_name = "mpu",
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|
.prcm = {
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|
.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_SR1_SHIFT,
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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|
.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
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|
},
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|
},
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.slaves = omap3_sr1_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
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|
};
|
|
|
|
/* SR2 */
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static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
|
|
&omap3_l4_core__sr2,
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|
};
|
|
|
|
static struct omap_hwmod omap34xx_sr2_hwmod = {
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|
.name = "sr2_hwmod",
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|
.class = &omap34xx_smartreflex_hwmod_class,
|
|
.main_clk = "sr2_fck",
|
|
.vdd_name = "core",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_SR2_SHIFT,
|
|
.module_offs = WKUP_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3_sr2_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
|
|
CHIP_IS_OMAP3430ES3_0 |
|
|
CHIP_IS_OMAP3430ES3_1),
|
|
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
|
|
};
|
|
|
|
static struct omap_hwmod omap36xx_sr2_hwmod = {
|
|
.name = "sr2_hwmod",
|
|
.class = &omap36xx_smartreflex_hwmod_class,
|
|
.main_clk = "sr2_fck",
|
|
.vdd_name = "core",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_SR2_SHIFT,
|
|
.module_offs = WKUP_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3_sr2_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
|
|
};
|
|
|
|
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
|
&omap3xxx_l3_main_hwmod,
|
|
&omap3xxx_l4_core_hwmod,
|
|
&omap3xxx_l4_per_hwmod,
|
|
&omap3xxx_l4_wkup_hwmod,
|
|
&omap3xxx_mpu_hwmod,
|
|
&omap3xxx_iva_hwmod,
|
|
&omap3xxx_wd_timer2_hwmod,
|
|
&omap3xxx_uart1_hwmod,
|
|
&omap3xxx_uart2_hwmod,
|
|
&omap3xxx_uart3_hwmod,
|
|
&omap3xxx_uart4_hwmod,
|
|
&omap3xxx_i2c1_hwmod,
|
|
&omap3xxx_i2c2_hwmod,
|
|
&omap3xxx_i2c3_hwmod,
|
|
&omap34xx_sr1_hwmod,
|
|
&omap34xx_sr2_hwmod,
|
|
&omap36xx_sr1_hwmod,
|
|
&omap36xx_sr2_hwmod,
|
|
|
|
|
|
/* gpio class */
|
|
&omap3xxx_gpio1_hwmod,
|
|
&omap3xxx_gpio2_hwmod,
|
|
&omap3xxx_gpio3_hwmod,
|
|
&omap3xxx_gpio4_hwmod,
|
|
&omap3xxx_gpio5_hwmod,
|
|
&omap3xxx_gpio6_hwmod,
|
|
|
|
/* dma_system class*/
|
|
&omap3xxx_dma_system_hwmod,
|
|
NULL,
|
|
};
|
|
|
|
int __init omap3xxx_hwmod_init(void)
|
|
{
|
|
return omap_hwmod_init(omap3xxx_hwmods);
|
|
}
|