d4b34c6c84
S5P Samsung SoCs has a EPLL to support various PLL clock sources for other H/W blocks. Until now, to control EPLL, each of SoCs make their own functions in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and 'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move these duplicated codes to common EPLL functions that use platform wide. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
92 lines
3.2 KiB
C
92 lines
3.2 KiB
C
/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV310 - Clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_CLOCK_H
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#define __ASM_ARCH_REGS_CLOCK_H __FILE__
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#include <mach/map.h>
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#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
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#define S5P_INFORM0 S5P_CLKREG(0x800)
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#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
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#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
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#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
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#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
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#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
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#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
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#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
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#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
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#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
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#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
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#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
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#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
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#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
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#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
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#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
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#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
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#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
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#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
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#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
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#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
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#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
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#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
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#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
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#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
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#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
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#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
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#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
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#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
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#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
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#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
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#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
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#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
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#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
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#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
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#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
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#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
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#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
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#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
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#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
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#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
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#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
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#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
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#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
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#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
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#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
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#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
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#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
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#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
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#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
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#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
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#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
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#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
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#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
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#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
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#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
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/* Compatibility defines */
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#define S5P_EPLL_CON S5P_EPLL_CON0
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#endif /* __ASM_ARCH_REGS_CLOCK_H */
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