26ecbdea4b
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
232 lines
6.7 KiB
C
232 lines
6.7 KiB
C
/* $Id: processor.h,v 1.83 2002/02/10 06:04:33 davem Exp $
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* include/asm-sparc64/processor.h
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef __ASM_SPARC64_PROCESSOR_H
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#define __ASM_SPARC64_PROCESSOR_H
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/*
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* Sparc64 implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
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#include <linux/config.h>
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#include <asm/asi.h>
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#include <asm/a.out.h>
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#include <asm/pstate.h>
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#include <asm/ptrace.h>
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#include <asm/page.h>
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/* The sparc has no problems with write protection */
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#define wp_works_ok 1
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#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
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/*
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* User lives in his very own context, and cannot reference us. Note
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* that TASK_SIZE is a misnomer, it really gives maximum user virtual
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* address that the kernel will allocate out.
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*/
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#define VA_BITS 44
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#ifndef __ASSEMBLY__
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#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
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#else
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#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
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#endif
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#define TASK_SIZE ((unsigned long)-VPTE_SIZE)
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/*
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* The vpte base must be able to hold the entire vpte, half
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* of which lives above, and half below, the base. And it
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* is placed as close to the highest address range as possible.
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*/
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#define VPTE_BASE_SPITFIRE (-(VPTE_SIZE/2))
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#if 1
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#define VPTE_BASE_CHEETAH VPTE_BASE_SPITFIRE
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#else
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#define VPTE_BASE_CHEETAH 0xffe0000000000000
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#endif
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#ifndef __ASSEMBLY__
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typedef struct {
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unsigned char seg;
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} mm_segment_t;
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/* The Sparc processor specific thread struct. */
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/* XXX This should die, everything can go into thread_info now. */
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struct thread_struct {
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#ifdef CONFIG_DEBUG_SPINLOCK
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/* How many spinlocks held by this thread.
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* Used with spin lock debugging to catch tasks
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* sleeping illegally with locks held.
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*/
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int smp_lock_count;
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unsigned int smp_lock_pc;
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#else
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int dummy; /* f'in gcc bug... */
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#endif
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};
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#endif /* !(__ASSEMBLY__) */
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#ifndef CONFIG_DEBUG_SPINLOCK
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#define INIT_THREAD { \
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0, \
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}
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#else /* CONFIG_DEBUG_SPINLOCK */
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#define INIT_THREAD { \
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/* smp_lock_count, smp_lock_pc, */ \
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0, 0, \
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}
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#endif /* !(CONFIG_DEBUG_SPINLOCK) */
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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/* Return saved PC of a blocked thread. */
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struct task_struct;
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extern unsigned long thread_saved_pc(struct task_struct *);
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/* On Uniprocessor, even in RMO processes see TSO semantics */
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#ifdef CONFIG_SMP
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#define TSTATE_INITIAL_MM TSTATE_TSO
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#else
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#define TSTATE_INITIAL_MM TSTATE_RMO
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#endif
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/* Do necessary setup to start up a newly executed thread. */
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#define start_thread(regs, pc, sp) \
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do { \
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regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (ASI_PNF << 24); \
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regs->tpc = ((pc & (~3)) - 4); \
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regs->tnpc = regs->tpc + 4; \
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regs->y = 0; \
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set_thread_wstate(1 << 3); \
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if (current_thread_info()->utraps) { \
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if (*(current_thread_info()->utraps) < 2) \
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kfree(current_thread_info()->utraps); \
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else \
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(*(current_thread_info()->utraps))--; \
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current_thread_info()->utraps = NULL; \
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} \
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__asm__ __volatile__( \
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"stx %%g0, [%0 + %2 + 0x00]\n\t" \
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"stx %%g0, [%0 + %2 + 0x08]\n\t" \
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"stx %%g0, [%0 + %2 + 0x10]\n\t" \
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"stx %%g0, [%0 + %2 + 0x18]\n\t" \
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"stx %%g0, [%0 + %2 + 0x20]\n\t" \
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"stx %%g0, [%0 + %2 + 0x28]\n\t" \
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"stx %%g0, [%0 + %2 + 0x30]\n\t" \
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"stx %%g0, [%0 + %2 + 0x38]\n\t" \
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"stx %%g0, [%0 + %2 + 0x40]\n\t" \
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"stx %%g0, [%0 + %2 + 0x48]\n\t" \
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"stx %%g0, [%0 + %2 + 0x50]\n\t" \
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"stx %%g0, [%0 + %2 + 0x58]\n\t" \
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"stx %%g0, [%0 + %2 + 0x60]\n\t" \
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"stx %%g0, [%0 + %2 + 0x68]\n\t" \
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"stx %1, [%0 + %2 + 0x70]\n\t" \
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"stx %%g0, [%0 + %2 + 0x78]\n\t" \
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"wrpr %%g0, (1 << 3), %%wstate\n\t" \
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: \
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: "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
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"i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
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} while (0)
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#define start_thread32(regs, pc, sp) \
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do { \
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pc &= 0x00000000ffffffffUL; \
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sp &= 0x00000000ffffffffUL; \
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\
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regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM); \
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regs->tpc = ((pc & (~3)) - 4); \
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regs->tnpc = regs->tpc + 4; \
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regs->y = 0; \
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set_thread_wstate(2 << 3); \
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if (current_thread_info()->utraps) { \
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if (*(current_thread_info()->utraps) < 2) \
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kfree(current_thread_info()->utraps); \
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else \
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(*(current_thread_info()->utraps))--; \
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current_thread_info()->utraps = NULL; \
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} \
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__asm__ __volatile__( \
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"stx %%g0, [%0 + %2 + 0x00]\n\t" \
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"stx %%g0, [%0 + %2 + 0x08]\n\t" \
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"stx %%g0, [%0 + %2 + 0x10]\n\t" \
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"stx %%g0, [%0 + %2 + 0x18]\n\t" \
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"stx %%g0, [%0 + %2 + 0x20]\n\t" \
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"stx %%g0, [%0 + %2 + 0x28]\n\t" \
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"stx %%g0, [%0 + %2 + 0x30]\n\t" \
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"stx %%g0, [%0 + %2 + 0x38]\n\t" \
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"stx %%g0, [%0 + %2 + 0x40]\n\t" \
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"stx %%g0, [%0 + %2 + 0x48]\n\t" \
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"stx %%g0, [%0 + %2 + 0x50]\n\t" \
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"stx %%g0, [%0 + %2 + 0x58]\n\t" \
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"stx %%g0, [%0 + %2 + 0x60]\n\t" \
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"stx %%g0, [%0 + %2 + 0x68]\n\t" \
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"stx %1, [%0 + %2 + 0x70]\n\t" \
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"stx %%g0, [%0 + %2 + 0x78]\n\t" \
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"wrpr %%g0, (2 << 3), %%wstate\n\t" \
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: \
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: "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
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"i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
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} while (0)
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/* Free all resources held by a thread. */
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#define release_thread(tsk) do { } while (0)
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/* Prepare to copy thread state - unlazy all lazy status */
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#define prepare_to_copy(tsk) do { } while (0)
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extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
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extern unsigned long get_wchan(struct task_struct *task);
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#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
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#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
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#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
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#define cpu_relax() barrier()
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/* Prefetch support. This is tuned for UltraSPARC-III and later.
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* UltraSPARC-I will treat these as nops, and UltraSPARC-II has
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* a shallower prefetch queue than later chips.
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*/
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#define ARCH_HAS_PREFETCH
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#define ARCH_HAS_PREFETCHW
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#define ARCH_HAS_SPINLOCK_PREFETCH
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static inline void prefetch(const void *x)
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{
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/* We do not use the read prefetch mnemonic because that
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* prefetches into the prefetch-cache which only is accessible
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* by floating point operations in UltraSPARC-III and later.
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* By contrast, "#one_write" prefetches into the L2 cache
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* in shared state.
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*/
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__asm__ __volatile__("prefetch [%0], #one_write"
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: /* no outputs */
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: "r" (x));
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}
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static inline void prefetchw(const void *x)
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{
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/* The most optimal prefetch to use for writes is
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* "#n_writes". This brings the cacheline into the
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* L2 cache in "owned" state.
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*/
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__asm__ __volatile__("prefetch [%0], #n_writes"
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: /* no outputs */
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: "r" (x));
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}
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#define spin_lock_prefetch(x) prefetchw(x)
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
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