ac7473a179
- Core:
- Provide a new mechanism to create interrupt domains. The existing
interfaces have already too many parameters and it's a pain to expand
any of this for new required functionality.
The new function takes a pointer to a data structure as argument. The
data structure combines all existing parameters and allows for easy
extension.
The first extension for this is to handle the instantiation of
generic interrupt chips at the core level and to allow drivers to
provide extra init/exit callbacks.
This is necessary to do the full interrupt chip initialization before
the new domain is published, so that concurrent usage sites won't see
a half initialized interrupt domain. Similar problems exist on
teardown.
This has turned out to be a real problem due to the deferred and
parallel probing which was added in recent years.
Handling this at the core level allows to remove quite some accrued
boilerplate code in existing drivers and avoids horrible workarounds
at the driver level.
- The usual small improvements all over the place
- Drivers
- Add support for LAN966x OIC and RZ/Five SoC
- Split the STM ExtI driver into a microcontroller and a SMP version to
allow building the latter as a module for multi-platform kernels.
- Enable MSI support for Armada 370XP on platforms which do not support
IPIs.
- The usual small fixes and enhancements all over the place.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmaVJbUTHHRnbHhAbGlu
dXRyb25peC5kZQAKCRCmGPVMDXSYoXTuD/9Tc9BhY5CW7HQkdPQu2Db1O+esprkQ
Uo9lMpTTpPiy9btg4LONzLf4mjbufZpyKBxkRWoZFO0Zj5q4UE9NZYh7EcxrF5Tl
CIFJmyteLsYuOyCmPrtSDSovonXjQKYBE3u2LVJNNkwEkhYbYW9sqIKeT8nneLv6
53gd28ESFUEUjHNTblw/eXviweyUKSXc0qyg+3hgZQPMoh9RkdkEPvyaw9Y/s5Ce
FelLLxzMqX86dR2TJMLqiaGiMpUu/kl+Yz2m5c77TwA2D68qjhHywbtKtlH7b3C6
LMHu2dMrrKSJrLL8roVIYJdHAd1TKWVdnYhqv9WBHFTu1sDuztpR44mewbo8exUU
L2RgVSGYNmeFC3p4wztWYSQfIVa9uOg7+TnJJdh7G0jLIeKM/TbufWqDAJAuoVPL
QhGbZ5xNbZJZ8bvhhItjxpRN/kPs44p3mUGyRJBQzm+mDN118bqfmQzhLcwRbfE2
smp73SQzg9alG2rGdNVEqkKmp8zhg2Crx2VCeVdgbeOxWQRet9zLWcp4FfCEUE9e
eK3iEi8z+rmwafaf3rsxYdrdIRLaUmcni0v7R/16cJH/Cs7bU3Re8XyGhevo3lsO
pJiP5wZDxbckwXNpLm3S/qPDW7vSCnuFPF7QmOvC3a70PsD+E4NKUgiwJuHtn/ZV
pFBKzbQgCsowQA==
=QCRH
-----END PGP SIGNATURE-----
Merge tag 'irq-core-2024-07-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull interrupt subsystem updates from Thomas Gleixner:
"Core:
- Provide a new mechanism to create interrupt domains. The existing
interfaces have already too many parameters and it's a pain to
expand any of this for new required functionality.
The new function takes a pointer to a data structure as argument.
The data structure combines all existing parameters and allows for
easy extension.
The first extension for this is to handle the instantiation of
generic interrupt chips at the core level and to allow drivers to
provide extra init/exit callbacks.
This is necessary to do the full interrupt chip initialization
before the new domain is published, so that concurrent usage sites
won't see a half initialized interrupt domain. Similar problems
exist on teardown.
This has turned out to be a real problem due to the deferred and
parallel probing which was added in recent years.
Handling this at the core level allows to remove quite some accrued
boilerplate code in existing drivers and avoids horrible
workarounds at the driver level.
- The usual small improvements all over the place
Drivers:
- Add support for LAN966x OIC and RZ/Five SoC
- Split the STM ExtI driver into a microcontroller and a SMP version
to allow building the latter as a module for multi-platform
kernels
- Enable MSI support for Armada 370XP on platforms which do not
support IPIs
- The usual small fixes and enhancements all over the place"
* tag 'irq-core-2024-07-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (59 commits)
irqdomain: Fix the kernel-doc and plug it into Documentation
genirq: Set IRQF_COND_ONESHOT in request_irq()
irqchip/imx-irqsteer: Handle runtime power management correctly
irqchip/gic-v3: Pass #redistributor-regions to gic_of_setup_kvm_info()
irqchip/bcm2835: Enable SKIP_SET_WAKE and MASK_ON_SUSPEND
irqchip/gic-v4: Make sure a VPE is locked when VMAPP is issued
irqchip/gic-v4: Substitute vmovp_lock for a per-VM lock
irqchip/gic-v4: Always configure affinity on VPE activation
Revert "irqchip/dw-apb-ictl: Support building as module"
Revert "Loongarch: Support loongarch avec"
arm64: Kconfig: Allow build irq-stm32mp-exti driver as module
ARM: stm32: Allow build irq-stm32mp-exti driver as module
irqchip/stm32mp-exti: Allow building as module
irqchip/stm32mp-exti: Rename internal symbols
irqchip/stm32-exti: Split MCU and MPU code
arm64: Kconfig: Select STM32MP_EXTI on STM32 platforms
ARM: stm32: Use different EXTI driver on ARMv7m and ARMv7a
irqchip/stm32-exti: Add CONFIG_STM32MP_EXTI
irqchip/dw-apb-ictl: Support building as module
irqchip/riscv-aplic: Simplify the initialization code
...
400 lines
9.4 KiB
Plaintext
400 lines
9.4 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menu "Platform selection"
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config ARCH_ACTIONS
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bool "Actions Semi Platforms"
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select OWL_TIMER
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select PINCTRL
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help
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This enables support for the Actions Semiconductor S900 SoC family.
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config ARCH_AIROHA
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bool "Airoha SoC Support"
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select ARM_PSCI
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select HAVE_ARM_ARCH_TIMER
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help
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This enables support for the ARM64 based Airoha SoCs.
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config ARCH_SUNXI
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bool "Allwinner sunxi 64-bit SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select PINCTRL
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select RESET_CONTROLLER
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select SUN4I_TIMER
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select SUN6I_R_INTC
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select SUNXI_NMI_INTC
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help
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This enables support for Allwinner sunxi based SoCs like the A64.
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config ARCH_ALPINE
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bool "Annapurna Labs Alpine platform"
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select ALPINE_MSI if PCI
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help
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This enables support for the Annapurna Labs Alpine
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Soc family.
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config ARCH_APPLE
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bool "Apple Silicon SoC family"
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select APPLE_AIC
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help
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This enables support for Apple's in-house ARM SoC family, starting
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with the Apple M1.
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menuconfig ARCH_BCM
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bool "Broadcom SoC Support"
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if ARCH_BCM
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config ARCH_BCM2835
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bool "Broadcom BCM2835 family"
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select TIMER_OF
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select GPIOLIB
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select MFD_CORE
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select PINCTRL
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select PINCTRL_BCM2835
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select ARM_AMBA
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select ARM_GIC
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select ARM_TIMER_SP804
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help
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This enables support for the Broadcom BCM2837 and BCM2711 SoC.
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These SoCs are used in the Raspberry Pi 3 and 4 devices.
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config ARCH_BCM_IPROC
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bool "Broadcom iProc SoC Family"
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select COMMON_CLK_IPROC
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select GPIOLIB
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select PINCTRL
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help
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This enables support for Broadcom iProc based SoCs
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config ARCH_BCMBCA
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bool "Broadcom Broadband Carrier Access (BCA) origin SoC"
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select GPIOLIB
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help
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Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
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BCA chipset.
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This enables support for Broadcom BCA ARM-based broadband chipsets,
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including the DSL, PON and Wireless family of chips.
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config ARCH_BRCMSTB
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bool "Broadcom Set-Top-Box SoCs"
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select ARCH_HAS_RESET_CONTROLLER
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select GENERIC_IRQ_CHIP
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select PINCTRL
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help
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This enables support for Broadcom's ARMv8 Set Top Box SoCs
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endif
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config ARCH_BERLIN
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bool "Marvell Berlin SoC Family"
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select DW_APB_ICTL
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select DW_APB_TIMER_OF
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select GPIOLIB
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select PINCTRL
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help
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This enables support for Marvell Berlin SoC Family
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config ARCH_BITMAIN
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bool "Bitmain SoC Platforms"
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help
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This enables support for the Bitmain SoC Family.
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config ARCH_EXYNOS
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bool "Samsung Exynos SoC family"
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select COMMON_CLK_SAMSUNG
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select CLKSRC_EXYNOS_MCT
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select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
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select EXYNOS_PMU
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select PINCTRL
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select PINCTRL_EXYNOS
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select PM_GENERIC_DOMAINS if PM
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select SOC_SAMSUNG
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help
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This enables support for ARMv8 based Samsung Exynos SoC family.
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config ARCH_SPARX5
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bool "Microchip Sparx5 SoC family"
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select PINCTRL
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select DW_APB_TIMER_OF
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help
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This enables support for the Microchip Sparx5 ARMv8-based
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SoC family of TSN-capable gigabit switches.
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The SparX-5 Ethernet switch family provides a rich set of
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switching features such as advanced TCAM-based VLAN and QoS
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processing enabling delivery of differentiated services, and
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security through TCAM-based frame processing using versatile
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content aware processor (VCAP).
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config ARCH_K3
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bool "Texas Instruments Inc. K3 multicore SoC architecture"
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select PM_GENERIC_DOMAINS if PM
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select MAILBOX
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select SOC_TI
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select TI_MESSAGE_MANAGER
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select TI_SCI_PROTOCOL
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select TI_SCI_INTR_IRQCHIP
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select TI_SCI_INTA_IRQCHIP
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select TI_K3_SOCINFO
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help
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This enables support for Texas Instruments' K3 multicore SoC
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architecture.
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config ARCH_LG1K
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bool "LG Electronics LG1K SoC Family"
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help
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This enables support for LG Electronics LG1K SoC Family
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config ARCH_HISI
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bool "Hisilicon SoC Family"
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select ARM_TIMER_SP804
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select HISILICON_IRQ_MBIGEN if PCI
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select PINCTRL
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help
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This enables support for Hisilicon ARMv8 SoC family
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config ARCH_KEEMBAY
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bool "Keem Bay SoC"
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help
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This enables support for Intel Movidius SoC code-named Keem Bay.
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config ARCH_MEDIATEK
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bool "MediaTek SoC Family"
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select ARM_GIC
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select PINCTRL
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select MTK_TIMER
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help
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This enables support for MediaTek MT27xx, MT65xx, MT76xx
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& MT81xx ARMv8 SoCs
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config ARCH_MESON
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bool "Amlogic Platforms"
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help
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This enables support for the arm64 based Amlogic SoCs
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such as the s905, S905X/D, S912, A113X/D or S905X/D2
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config ARCH_MVEBU
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bool "Marvell EBU SoC Family"
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select ARMADA_AP806_SYSCON
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select ARMADA_CP110_SYSCON
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select ARMADA_37XX_CLK
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select MVEBU_GICP
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select MVEBU_ICU
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select MVEBU_ODMI
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select MVEBU_PIC
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select MVEBU_SEI
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select OF_GPIO
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select PINCTRL
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select PINCTRL_ARMADA_37XX
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select PINCTRL_ARMADA_AP806
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select PINCTRL_ARMADA_CP110
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select PINCTRL_AC5
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help
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This enables support for Marvell EBU family, including:
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- Armada 3700 SoC Family
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- Armada 7K SoC Family
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- Armada 8K SoC Family
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- 98DX2530 SoC Family
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menuconfig ARCH_NXP
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bool "NXP SoC support"
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if ARCH_NXP
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config ARCH_LAYERSCAPE
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bool "Freescale Layerscape SoC family"
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help
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This enables support for the Freescale Layerscape SoC family.
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config ARCH_MXC
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bool "NXP i.MX SoC family"
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select ARM64_ERRATUM_843419
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select ARM64_ERRATUM_845719 if COMPAT
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select IMX_GPCV2
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select IMX_GPCV2_PM_DOMAINS
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select PM
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select PM_GENERIC_DOMAINS
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select SOC_BUS
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select TIMER_IMX_SYS_CTR
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help
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This enables support for the ARMv8 based SoCs in the
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NXP i.MX family.
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config ARCH_S32
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bool "NXP S32 SoC Family"
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help
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This enables support for the NXP S32 family of processors.
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endif
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config ARCH_MA35
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bool "Nuvoton MA35 Architecture"
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select GPIOLIB
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select PINCTRL
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select RESET_CONTROLLER
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help
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This enables support for the ARMv8 based Nuvoton MA35 series SoCs.
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config ARCH_NPCM
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bool "Nuvoton NPCM Architecture"
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select PINCTRL
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select GPIOLIB
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select NPCM7XX_TIMER
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select RESET_CONTROLLER
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select MFD_SYSCON
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help
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General support for NPCM8xx BMC (Arbel).
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Nuvoton NPCM8xx BMC based on the Cortex A35.
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config ARCH_PENSANDO
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bool "AMD Pensando Platforms"
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help
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This enables support for the ARMv8 based AMD Pensando SoC
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family to include the Elba SoC.
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AMD Pensando SoCs support a range of Distributed Services
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Cards in PCIe format installed into servers. The Elba
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SoC includes 16 Cortex A-72 CPU cores, 144 P4-programmable
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cores for a minimal latency/jitter datapath, and network
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interfaces up to 200 Gb/s.
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config ARCH_QCOM
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bool "Qualcomm Platforms"
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select GPIOLIB
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select PINCTRL
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select HAVE_PWRCTL if PCI
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help
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This enables support for the ARMv8 based Qualcomm chipsets.
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config ARCH_REALTEK
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bool "Realtek Platforms"
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select RESET_CONTROLLER
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help
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This enables support for the ARMv8 based Realtek chipsets,
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like the RTD1295.
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config ARCH_RENESAS
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bool "Renesas SoC Platforms"
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help
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This enables support for the ARMv8 based Renesas SoCs.
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config ARCH_ROCKCHIP
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bool "Rockchip Platforms"
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select ARCH_HAS_RESET_CONTROLLER
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select PINCTRL
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select PM
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select ROCKCHIP_TIMER
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help
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This enables support for the ARMv8 based Rockchip chipsets,
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like the RK3368.
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config ARCH_SEATTLE
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bool "AMD Seattle SoC Family"
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help
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This enables support for AMD Seattle SOC Family
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config ARCH_INTEL_SOCFPGA
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bool "Intel's SoCFPGA ARMv8 Families"
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help
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This enables support for Intel's SoCFPGA ARMv8 families:
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Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
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Agilex and eASIC N5X.
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config ARCH_STM32
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bool "STMicroelectronics STM32 SoC Family"
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select GPIOLIB
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select PINCTRL
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select PINCTRL_STM32MP257
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select ARM_SMC_MBOX
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select ARM_SCMI_PROTOCOL
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select REGULATOR
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select REGULATOR_ARM_SCMI
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select COMMON_CLK_SCMI
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select STM32_FIREWALL
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help
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This enables support for ARMv8 based STMicroelectronics
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STM32 family, including:
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- STM32MP25:
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- STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
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config ARCH_SYNQUACER
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bool "Socionext SynQuacer SoC Family"
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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config ARCH_TEGRA
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bool "NVIDIA Tegra SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_GIC_PM
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select CLKSRC_MMIO
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select TIMER_OF
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select GPIOLIB
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select PINCTRL
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select PM
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select PM_GENERIC_DOMAINS
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select RESET_CONTROLLER
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help
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This enables support for the NVIDIA Tegra SoC family.
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config ARCH_TESLA_FSD
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bool "Tesla platform"
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depends on ARCH_EXYNOS
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help
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Support for ARMv8 based Tesla platforms.
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config ARCH_SPRD
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bool "Spreadtrum SoC platform"
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help
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Support for Spreadtrum ARM based SoCs
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config ARCH_THUNDER
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bool "Cavium Inc. Thunder SoC Family"
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help
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This enables support for Cavium's Thunder Family of SoCs.
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config ARCH_THUNDER2
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bool "Cavium ThunderX2 Server Processors"
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select GPIOLIB
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help
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This enables support for Cavium's ThunderX2 CN99XX family of
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server processors.
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config ARCH_UNIPHIER
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bool "Socionext UniPhier SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select PINCTRL
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select RESET_CONTROLLER
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help
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This enables support for Socionext UniPhier SoC family.
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config ARCH_VEXPRESS
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bool "ARMv8 software model (Versatile Express)"
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select GPIOLIB
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select PM
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select PM_GENERIC_DOMAINS
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help
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This enables support for the ARMv8 software model (Versatile
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Express).
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config ARCH_VISCONTI
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bool "Toshiba Visconti SoC Family"
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select PINCTRL
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select PINCTRL_VISCONTI
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help
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This enables support for Toshiba Visconti SoCs Family.
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config ARCH_XGENE
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bool "AppliedMicro X-Gene SOC Family"
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help
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This enables support for AppliedMicro X-Gene SOC Family
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config ARCH_ZYNQMP
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bool "Xilinx ZynqMP Family"
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help
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This enables support for Xilinx ZynqMP Family
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endmenu # "Platform selection"
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