b09bcdd4c2
The S3C64XX series has a new TCFG divider setting to allow the clock directly through, which means that we need to update the pwm-clock code to cope with this. Add <mach/pwm-clock.h> containing the specific code to deal with the TCFG divider settings and provide any other per-arch data that the pwm-clock driver needs to function. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
125 lines
4.0 KiB
C
125 lines
4.0 KiB
C
/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
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*
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* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 Timer configuration
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*/
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#ifndef __ASM_ARCH_REGS_TIMER_H
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#define __ASM_ARCH_REGS_TIMER_H
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#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
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#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
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#define S3C2410_TCFG0 S3C_TIMERREG(0x00)
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#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
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#define S3C2410_TCON S3C_TIMERREG(0x08)
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#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44)
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#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
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#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
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#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
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#define S3C2410_TCFG_DEADZONE_MASK (255<<16)
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#define S3C2410_TCFG_DEADZONE_SHIFT (16)
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#define S3C2410_TCFG1_MUX4_DIV2 (0<<16)
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#define S3C2410_TCFG1_MUX4_DIV4 (1<<16)
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#define S3C2410_TCFG1_MUX4_DIV8 (2<<16)
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#define S3C2410_TCFG1_MUX4_DIV16 (3<<16)
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#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16)
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#define S3C2410_TCFG1_MUX4_MASK (15<<16)
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#define S3C2410_TCFG1_MUX4_SHIFT (16)
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#define S3C2410_TCFG1_MUX3_DIV2 (0<<12)
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#define S3C2410_TCFG1_MUX3_DIV4 (1<<12)
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#define S3C2410_TCFG1_MUX3_DIV8 (2<<12)
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#define S3C2410_TCFG1_MUX3_DIV16 (3<<12)
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#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12)
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#define S3C2410_TCFG1_MUX3_MASK (15<<12)
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#define S3C2410_TCFG1_MUX2_DIV2 (0<<8)
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#define S3C2410_TCFG1_MUX2_DIV4 (1<<8)
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#define S3C2410_TCFG1_MUX2_DIV8 (2<<8)
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#define S3C2410_TCFG1_MUX2_DIV16 (3<<8)
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#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8)
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#define S3C2410_TCFG1_MUX2_MASK (15<<8)
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#define S3C2410_TCFG1_MUX1_DIV2 (0<<4)
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#define S3C2410_TCFG1_MUX1_DIV4 (1<<4)
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#define S3C2410_TCFG1_MUX1_DIV8 (2<<4)
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#define S3C2410_TCFG1_MUX1_DIV16 (3<<4)
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#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4)
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#define S3C2410_TCFG1_MUX1_MASK (15<<4)
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#define S3C2410_TCFG1_MUX0_DIV2 (0<<0)
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#define S3C2410_TCFG1_MUX0_DIV4 (1<<0)
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#define S3C2410_TCFG1_MUX0_DIV8 (2<<0)
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#define S3C2410_TCFG1_MUX0_DIV16 (3<<0)
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#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
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#define S3C2410_TCFG1_MUX0_MASK (15<<0)
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#define S3C2410_TCFG1_MUX_DIV2 (0<<0)
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#define S3C2410_TCFG1_MUX_DIV4 (1<<0)
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#define S3C2410_TCFG1_MUX_DIV8 (2<<0)
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#define S3C2410_TCFG1_MUX_DIV16 (3<<0)
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#define S3C2410_TCFG1_MUX_TCLK (4<<0)
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#define S3C2410_TCFG1_MUX_MASK (15<<0)
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#define S3C64XX_TCFG1_MUX_DIV1 (0<<0)
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#define S3C64XX_TCFG1_MUX_DIV2 (1<<0)
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#define S3C64XX_TCFG1_MUX_DIV4 (2<<0)
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#define S3C64XX_TCFG1_MUX_DIV8 (3<<0)
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#define S3C64XX_TCFG1_MUX_DIV16 (4<<0)
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#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */
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#define S3C64XX_TCFG1_MUX_MASK (15<<0)
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#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
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/* for each timer, we have an count buffer, an compare buffer and
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* an observation buffer
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*/
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/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
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#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
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#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
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#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
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#define S3C2410_TCON_T4RELOAD (1<<22)
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#define S3C2410_TCON_T4MANUALUPD (1<<21)
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#define S3C2410_TCON_T4START (1<<20)
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#define S3C2410_TCON_T3RELOAD (1<<19)
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#define S3C2410_TCON_T3INVERT (1<<18)
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#define S3C2410_TCON_T3MANUALUPD (1<<17)
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#define S3C2410_TCON_T3START (1<<16)
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#define S3C2410_TCON_T2RELOAD (1<<15)
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#define S3C2410_TCON_T2INVERT (1<<14)
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#define S3C2410_TCON_T2MANUALUPD (1<<13)
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#define S3C2410_TCON_T2START (1<<12)
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#define S3C2410_TCON_T1RELOAD (1<<11)
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#define S3C2410_TCON_T1INVERT (1<<10)
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#define S3C2410_TCON_T1MANUALUPD (1<<9)
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#define S3C2410_TCON_T1START (1<<8)
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#define S3C2410_TCON_T0DEADZONE (1<<4)
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#define S3C2410_TCON_T0RELOAD (1<<3)
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#define S3C2410_TCON_T0INVERT (1<<2)
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#define S3C2410_TCON_T0MANUALUPD (1<<1)
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#define S3C2410_TCON_T0START (1<<0)
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#endif /* __ASM_ARCH_REGS_TIMER_H */
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