abf12d719a
Dynamically detect the DBx500 SOC an revision based on the ASIC ID. Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
130 lines
3.4 KiB
C
130 lines
3.4 KiB
C
/*
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* Copyright (C) 2008-2009 ST-Ericsson
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*
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* Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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#include <mach/devices.h>
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#include "devices-db8500.h"
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static struct platform_device *platform_devs[] __initdata = {
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&u8500_dma40_device,
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};
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/* minimum static i/o mapping required to boot U8500 platforms */
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static struct map_desc u8500_uart_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
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};
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static struct map_desc u8500_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_TWD_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
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__IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
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};
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static struct map_desc u8500_ed_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K),
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};
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static struct map_desc u8500_v1_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K),
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};
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static struct map_desc u8500_v2_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
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};
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void __init u8500_map_io(void)
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{
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/*
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* Map the UARTs early so that the DEBUG_LL stuff continues to work.
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*/
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iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
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ux500_map_io();
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iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
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if (cpu_is_u8500ed())
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iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
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else if (cpu_is_u8500v1())
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iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
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else if (cpu_is_u8500v2())
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iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
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}
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static resource_size_t __initdata db8500_gpio_base[] = {
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U8500_GPIOBANK0_BASE,
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U8500_GPIOBANK1_BASE,
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U8500_GPIOBANK2_BASE,
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U8500_GPIOBANK3_BASE,
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U8500_GPIOBANK4_BASE,
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U8500_GPIOBANK5_BASE,
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U8500_GPIOBANK6_BASE,
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U8500_GPIOBANK7_BASE,
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U8500_GPIOBANK8_BASE,
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};
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static void __init db8500_add_gpios(void)
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{
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struct nmk_gpio_platform_data pdata = {
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/* No custom data yet */
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};
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dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
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IRQ_DB8500_GPIO0, &pdata);
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}
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/*
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* This function is called from the board init
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*/
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void __init u8500_init_devices(void)
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{
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if (cpu_is_u8500ed())
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dma40_u8500ed_fixup();
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db8500_add_rtc();
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db8500_add_gpios();
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platform_device_register_simple("cpufreq-u8500", -1, NULL, 0);
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platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
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return ;
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}
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