On most tg3 chips, the memory enable bit in the PCI command register
gets cleared during chip reset and must be restored before accessing
PCI registers using memory cycles. The chip does not generate
interrupt during chip reset, but the irq handler can still be called
because of irq sharing or irqpoll. Reading a register in the irq
handler can cause a master abort in this scenario and may result in a
crash on some architectures.
Use the TG3_FLAG_CHIP_RESETTING flag to tell the irq handler to exit
without touching any registers. The checking of the flag is in the
"slow" path of the irq handler and will not affect normal performance.
The msi handler is not shared and therefore does not require checking
the flag.
Thanks to Bernhard Walle <bwalle@suse.de> for reporting the problem.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
d18edcb212