7358a803c7
The Output Processing Engine (OPE) is one of the AHUB client. It has PEQ (Parametric Equalizer) and MBDRC (Multi Band Dynamic Range Compressor) sub blocks for data processing. The PEQ block gets samples from the MBDRC block. This patch registers OPE driver with ASoC framework. The component driver exposes DAPM widgets, routes and kcontrols for the device. The DAI driver exposes OPE interfaces, which can be used to connect different components in the ASoC layer. Makefile and Kconfig support is added to allow build the driver. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Link: https://lore.kernel.org/r/1654238172-16293-3-git-send-email-spujar@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_ope.h - Definitions for Tegra210 OPE driver
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*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA210_OPE_H__
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#define __TEGRA210_OPE_H__
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#include <linux/regmap.h>
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#include <sound/soc.h>
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#include "tegra210_peq.h"
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/*
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* OPE_RX registers are with respect to XBAR.
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* The data comes from XBAR to OPE
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*/
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#define TEGRA210_OPE_RX_STATUS 0xc
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#define TEGRA210_OPE_RX_INT_STATUS 0x10
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#define TEGRA210_OPE_RX_INT_MASK 0x14
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#define TEGRA210_OPE_RX_INT_SET 0x18
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#define TEGRA210_OPE_RX_INT_CLEAR 0x1c
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#define TEGRA210_OPE_RX_CIF_CTRL 0x20
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/*
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* OPE_TX registers are with respect to XBAR.
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* The data goes out from OPE to XBAR
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*/
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#define TEGRA210_OPE_TX_STATUS 0x4c
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#define TEGRA210_OPE_TX_INT_STATUS 0x50
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#define TEGRA210_OPE_TX_INT_MASK 0x54
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#define TEGRA210_OPE_TX_INT_SET 0x58
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#define TEGRA210_OPE_TX_INT_CLEAR 0x5c
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#define TEGRA210_OPE_TX_CIF_CTRL 0x60
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/* OPE Gloabal registers */
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#define TEGRA210_OPE_ENABLE 0x80
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#define TEGRA210_OPE_SOFT_RESET 0x84
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#define TEGRA210_OPE_CG 0x88
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#define TEGRA210_OPE_STATUS 0x8c
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#define TEGRA210_OPE_INT_STATUS 0x90
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#define TEGRA210_OPE_DIR 0x94
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/* Fields for TEGRA210_OPE_ENABLE */
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#define TEGRA210_OPE_EN_SHIFT 0
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#define TEGRA210_OPE_EN (1 << TEGRA210_OPE_EN_SHIFT)
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/* Fields for TEGRA210_OPE_SOFT_RESET */
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#define TEGRA210_OPE_SOFT_RESET_SHIFT 0
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#define TEGRA210_OPE_SOFT_RESET_EN (1 << TEGRA210_OPE_SOFT_RESET_SHIFT)
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#define TEGRA210_OPE_DIR_SHIFT 0
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struct tegra210_ope {
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struct regmap *regmap;
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struct regmap *peq_regmap;
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struct regmap *mbdrc_regmap;
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u32 peq_biquad_gains[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH];
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u32 peq_biquad_shifts[TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH];
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unsigned int data_dir;
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};
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/* Extension of soc_bytes structure defined in sound/soc.h */
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struct tegra_soc_bytes {
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struct soc_bytes soc;
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u32 shift; /* Used as offset for AHUB RAM related programing */
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};
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/* Utility structures for using mixer control of type snd_soc_bytes */
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#define TEGRA_SOC_BYTES_EXT(xname, xbase, xregs, xshift, xmask, \
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xhandler_get, xhandler_put, xinfo) \
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{ \
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
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.name = xname, \
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.info = xinfo, \
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.get = xhandler_get, \
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.put = xhandler_put, \
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.private_value = ((unsigned long)&(struct tegra_soc_bytes) \
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{ \
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.soc.base = xbase, \
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.soc.num_regs = xregs, \
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.soc.mask = xmask, \
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.shift = xshift \
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}) \
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}
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#endif
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