2502f8dd8c
The AHUB HW modules are interconnected with CIF which are capable of
supporting Channel and Sample bit format conversion. Due to this, the
I2S Client can have different Channel and Sample bit from the hw_params()
and this config is passed from CIF port of I2S DT node which can help to
perform this conversion.
For e.g. HFP usecase consists of BT SCO with 1ch and 8k audio data
which needs to be converted and mixed with external codec playback and
capture path which is of 2ch and 48k format.
For HFP Playback:
The path includes mono to stereo and 8k to 48k conversion
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
| |1ch | | 1ch | |2ch | SFC | 2ch | |
|BT SCO |---->| I2Sx |------>| CIF |----->| 8k->48k |---->| Codec I2Sy|
|_ _ _ _| |_ _ __|client |_ _ _|audio |_ _ _ _ _| |_ _ _ _ _ _|
For HFP Capture:
The path includes stereo to mono and 48k to 8k conversion
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
| | 2ch | SFC | 2ch | | 1ch | | 1ch | |
| codec I2Sy|---->| 48k->8k |----->| CIF |------>| I2Sx |---->| BT SCO|
|_ _ _ _ _ _| |_ _ _ _ _| audio|_ _ _|client |_ _ _ _| |_ _ _ _|
For above two path, I2S client channel uses existing DT binding to pass
channels and format conversion in I2Sx CIF Port.
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Link: https://msgid.link/r/20240527125608.2461300-3-spujar@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_i2s.h - Definitions for Tegra210 I2S driver
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*
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* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA210_I2S_H__
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#define __TEGRA210_I2S_H__
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/* Register offsets from I2S*_BASE */
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#define TEGRA210_I2S_RX_ENABLE 0x0
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#define TEGRA210_I2S_RX_SOFT_RESET 0x4
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#define TEGRA210_I2S_RX_STATUS 0x0c
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#define TEGRA210_I2S_RX_INT_STATUS 0x10
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#define TEGRA210_I2S_RX_INT_MASK 0x14
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#define TEGRA210_I2S_RX_INT_SET 0x18
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#define TEGRA210_I2S_RX_INT_CLEAR 0x1c
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#define TEGRA210_I2S_RX_CIF_CTRL 0x20
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#define TEGRA210_I2S_RX_CTRL 0x24
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#define TEGRA210_I2S_RX_SLOT_CTRL 0x28
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#define TEGRA210_I2S_RX_CLK_TRIM 0x2c
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#define TEGRA210_I2S_RX_CYA 0x30
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#define TEGRA210_I2S_RX_CIF_FIFO_STATUS 0x34
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#define TEGRA210_I2S_TX_ENABLE 0x40
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#define TEGRA210_I2S_TX_SOFT_RESET 0x44
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#define TEGRA210_I2S_TX_STATUS 0x4c
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#define TEGRA210_I2S_TX_INT_STATUS 0x50
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#define TEGRA210_I2S_TX_INT_MASK 0x54
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#define TEGRA210_I2S_TX_INT_SET 0x58
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#define TEGRA210_I2S_TX_INT_CLEAR 0x5c
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#define TEGRA210_I2S_TX_CIF_CTRL 0x60
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#define TEGRA210_I2S_TX_CTRL 0x64
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#define TEGRA210_I2S_TX_SLOT_CTRL 0x68
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#define TEGRA210_I2S_TX_CLK_TRIM 0x6c
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#define TEGRA210_I2S_TX_CYA 0x70
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#define TEGRA210_I2S_TX_CIF_FIFO_STATUS 0x74
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#define TEGRA210_I2S_ENABLE 0x80
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#define TEGRA210_I2S_SOFT_RESET 0x84
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#define TEGRA210_I2S_CG 0x88
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#define TEGRA210_I2S_STATUS 0x8c
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#define TEGRA210_I2S_INT_STATUS 0x90
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#define TEGRA210_I2S_CTRL 0xa0
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#define TEGRA210_I2S_TIMING 0xa4
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#define TEGRA210_I2S_SLOT_CTRL 0xa8
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#define TEGRA210_I2S_CLK_TRIM 0xac
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#define TEGRA210_I2S_CYA 0xb0
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/* Bit fields, shifts and masks */
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#define I2S_DATA_SHIFT 8
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#define I2S_CTRL_DATA_OFFSET_MASK (0x7ff << I2S_DATA_SHIFT)
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#define I2S_EN_SHIFT 0
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#define I2S_EN_MASK BIT(I2S_EN_SHIFT)
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#define I2S_EN BIT(I2S_EN_SHIFT)
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#define I2S_FSYNC_WIDTH_SHIFT 24
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#define I2S_CTRL_FSYNC_WIDTH_MASK (0xff << I2S_FSYNC_WIDTH_SHIFT)
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#define I2S_POS_EDGE 0
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#define I2S_NEG_EDGE 1
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#define I2S_EDGE_SHIFT 20
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#define I2S_CTRL_EDGE_CTRL_MASK BIT(I2S_EDGE_SHIFT)
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#define I2S_CTRL_EDGE_CTRL_POS_EDGE (I2S_POS_EDGE << I2S_EDGE_SHIFT)
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#define I2S_CTRL_EDGE_CTRL_NEG_EDGE (I2S_NEG_EDGE << I2S_EDGE_SHIFT)
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#define I2S_FMT_LRCK 0
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#define I2S_FMT_FSYNC 1
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#define I2S_FMT_SHIFT 12
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#define I2S_CTRL_FRAME_FMT_MASK (7 << I2S_FMT_SHIFT)
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#define I2S_CTRL_FRAME_FMT_LRCK_MODE (I2S_FMT_LRCK << I2S_FMT_SHIFT)
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#define I2S_CTRL_FRAME_FMT_FSYNC_MODE (I2S_FMT_FSYNC << I2S_FMT_SHIFT)
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#define I2S_CTRL_MASTER_EN_SHIFT 10
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#define I2S_CTRL_MASTER_EN_MASK BIT(I2S_CTRL_MASTER_EN_SHIFT)
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#define I2S_CTRL_MASTER_EN BIT(I2S_CTRL_MASTER_EN_SHIFT)
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#define I2S_CTRL_LRCK_POL_SHIFT 9
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#define I2S_CTRL_LRCK_POL_MASK BIT(I2S_CTRL_LRCK_POL_SHIFT)
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#define I2S_CTRL_LRCK_POL_LOW (0 << I2S_CTRL_LRCK_POL_SHIFT)
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#define I2S_CTRL_LRCK_POL_HIGH BIT(I2S_CTRL_LRCK_POL_SHIFT)
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#define I2S_CTRL_LPBK_SHIFT 8
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#define I2S_CTRL_LPBK_MASK BIT(I2S_CTRL_LPBK_SHIFT)
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#define I2S_CTRL_LPBK_EN BIT(I2S_CTRL_LPBK_SHIFT)
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#define I2S_BITS_8 1
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#define I2S_BITS_16 3
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#define I2S_BITS_32 7
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#define I2S_CTRL_BIT_SIZE_MASK 0x7
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#define I2S_TIMING_CH_BIT_CNT_MASK 0x7ff
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#define I2S_TIMING_CH_BIT_CNT_SHIFT 0
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#define I2S_SOFT_RESET_SHIFT 0
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#define I2S_SOFT_RESET_MASK BIT(I2S_SOFT_RESET_SHIFT)
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#define I2S_SOFT_RESET_EN BIT(I2S_SOFT_RESET_SHIFT)
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#define I2S_RX_FIFO_DEPTH 64
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#define DEFAULT_I2S_RX_FIFO_THRESHOLD 3
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#define DEFAULT_I2S_SLOT_MASK 0xffff
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enum tegra210_i2s_path {
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I2S_RX_PATH,
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I2S_TX_PATH,
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I2S_PATHS,
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};
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struct tegra210_i2s {
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struct clk *clk_i2s;
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struct clk *clk_sync_input;
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struct regmap *regmap;
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int client_sample_format;
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unsigned int client_channels;
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unsigned int stereo_to_mono[I2S_PATHS];
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unsigned int mono_to_stereo[I2S_PATHS];
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unsigned int dai_fmt;
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unsigned int fsync_width;
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unsigned int bclk_ratio;
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unsigned int tx_mask;
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unsigned int rx_mask;
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unsigned int rx_fifo_th;
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bool loopback;
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};
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#endif
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