b7ec7fd632
There's the limitation of Synopsys dwc3 controller with ERST programming in supporting separate ERSTBA_HI and ERSTBA_LO programming. It's supported when the ERSTBA is programmed ERSTBA_HI before ERSTBA_LO. But, writing operations in xHCI is done low-high order following xHCI spec. xHCI specification 5.1 "Register Conventions" states that 64 bit registers should be written in low-high order. Synopsys dwc3 needs workaround for high-low order. That's why adding new quirk is needed to support this. Signed-off-by: Daehwan Jung <dh10.jung@samsung.com> Link: https://lore.kernel.org/r/1718019553-111939-2-git-send-email-dh10.jung@samsung.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
227 lines
5.3 KiB
C
227 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* host.c - DesignWare USB3 DRD Controller Host Glue
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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*/
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include "../host/xhci-port.h"
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#include "../host/xhci-ext-caps.h"
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#include "../host/xhci-caps.h"
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#include "../host/xhci-plat.h"
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#include "core.h"
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#define XHCI_HCSPARAMS1 0x4
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#define XHCI_PORTSC_BASE 0x400
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/**
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* dwc3_power_off_all_roothub_ports - Power off all Root hub ports
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* @dwc: Pointer to our controller context structure
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*/
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static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc)
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{
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void __iomem *xhci_regs;
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u32 op_regs_base;
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int port_num;
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u32 offset;
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u32 reg;
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int i;
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/* xhci regs is not mapped yet, do it temperary here */
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if (dwc->xhci_resources[0].start) {
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xhci_regs = ioremap(dwc->xhci_resources[0].start, DWC3_XHCI_REGS_END);
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if (!xhci_regs) {
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dev_err(dwc->dev, "Failed to ioremap xhci_regs\n");
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return;
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}
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op_regs_base = HC_LENGTH(readl(xhci_regs));
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reg = readl(xhci_regs + XHCI_HCSPARAMS1);
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port_num = HCS_MAX_PORTS(reg);
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for (i = 1; i <= port_num; i++) {
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offset = op_regs_base + XHCI_PORTSC_BASE + 0x10 * (i - 1);
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reg = readl(xhci_regs + offset);
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reg &= ~PORT_POWER;
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writel(reg, xhci_regs + offset);
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}
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iounmap(xhci_regs);
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} else {
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dev_err(dwc->dev, "xhci base reg invalid\n");
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}
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}
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static void dwc3_xhci_plat_start(struct usb_hcd *hcd)
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{
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struct platform_device *pdev;
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struct dwc3 *dwc;
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if (!usb_hcd_is_primary_hcd(hcd))
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return;
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pdev = to_platform_device(hcd->self.controller);
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dwc = dev_get_drvdata(pdev->dev.parent);
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dwc3_enable_susphy(dwc, true);
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}
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static const struct xhci_plat_priv dwc3_xhci_plat_quirk = {
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.plat_start = dwc3_xhci_plat_start,
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};
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static void dwc3_host_fill_xhci_irq_res(struct dwc3 *dwc,
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int irq, char *name)
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{
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struct platform_device *pdev = to_platform_device(dwc->dev);
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struct device_node *np = dev_of_node(&pdev->dev);
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dwc->xhci_resources[1].start = irq;
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dwc->xhci_resources[1].end = irq;
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dwc->xhci_resources[1].flags = IORESOURCE_IRQ | irq_get_trigger_type(irq);
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if (!name && np)
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dwc->xhci_resources[1].name = of_node_full_name(pdev->dev.of_node);
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else
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dwc->xhci_resources[1].name = name;
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}
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static int dwc3_host_get_irq(struct dwc3 *dwc)
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{
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struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
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int irq;
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irq = platform_get_irq_byname_optional(dwc3_pdev, "host");
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if (irq > 0) {
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dwc3_host_fill_xhci_irq_res(dwc, irq, "host");
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goto out;
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}
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if (irq == -EPROBE_DEFER)
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goto out;
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irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
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if (irq > 0) {
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dwc3_host_fill_xhci_irq_res(dwc, irq, "dwc_usb3");
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goto out;
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}
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if (irq == -EPROBE_DEFER)
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goto out;
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irq = platform_get_irq(dwc3_pdev, 0);
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if (irq > 0)
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dwc3_host_fill_xhci_irq_res(dwc, irq, NULL);
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out:
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return irq;
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}
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int dwc3_host_init(struct dwc3 *dwc)
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{
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struct property_entry props[6];
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struct platform_device *xhci;
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int ret, irq;
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int prop_idx = 0;
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/*
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* Some platforms need to power off all Root hub ports immediately after DWC3 set to host
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* mode to avoid VBUS glitch happen when xhci get reset later.
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*/
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dwc3_power_off_all_roothub_ports(dwc);
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irq = dwc3_host_get_irq(dwc);
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if (irq < 0)
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return irq;
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xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO);
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if (!xhci) {
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dev_err(dwc->dev, "couldn't allocate xHCI device\n");
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return -ENOMEM;
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}
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xhci->dev.parent = dwc->dev;
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dwc->xhci = xhci;
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ret = platform_device_add_resources(xhci, dwc->xhci_resources,
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DWC3_XHCI_RESOURCES_NUM);
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if (ret) {
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dev_err(dwc->dev, "couldn't add resources to xHCI device\n");
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goto err;
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}
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memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
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props[prop_idx++] = PROPERTY_ENTRY_BOOL("xhci-sg-trb-cache-size-quirk");
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props[prop_idx++] = PROPERTY_ENTRY_BOOL("write-64-hi-lo-quirk");
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if (dwc->usb3_lpm_capable)
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props[prop_idx++] = PROPERTY_ENTRY_BOOL("usb3-lpm-capable");
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if (dwc->usb2_lpm_disable)
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props[prop_idx++] = PROPERTY_ENTRY_BOOL("usb2-lpm-disable");
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/**
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* WORKAROUND: dwc3 revisions <=3.00a have a limitation
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* where Port Disable command doesn't work.
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*
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* The suggested workaround is that we avoid Port Disable
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* completely.
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*
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* This following flag tells XHCI to do just that.
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*/
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if (DWC3_VER_IS_WITHIN(DWC3, ANY, 300A))
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props[prop_idx++] = PROPERTY_ENTRY_BOOL("quirk-broken-port-ped");
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if (prop_idx) {
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ret = device_create_managed_software_node(&xhci->dev, props, NULL);
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if (ret) {
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dev_err(dwc->dev, "failed to add properties to xHCI\n");
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goto err;
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}
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}
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ret = platform_device_add_data(xhci, &dwc3_xhci_plat_quirk,
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sizeof(struct xhci_plat_priv));
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if (ret)
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goto err;
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ret = platform_device_add(xhci);
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if (ret) {
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dev_err(dwc->dev, "failed to register xHCI device\n");
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goto err;
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}
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if (dwc->sys_wakeup) {
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/* Restore wakeup setting if switched from device */
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device_wakeup_enable(dwc->sysdev);
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/* Pass on wakeup setting to the new xhci platform device */
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device_init_wakeup(&xhci->dev, true);
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}
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return 0;
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err:
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platform_device_put(xhci);
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return ret;
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}
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void dwc3_host_exit(struct dwc3 *dwc)
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{
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if (dwc->sys_wakeup)
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device_init_wakeup(&dwc->xhci->dev, false);
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dwc3_enable_susphy(dwc, false);
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platform_device_unregister(dwc->xhci);
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dwc->xhci = NULL;
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}
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