05ecc67835
The LCDIF controller as present in i.MX28/i.MX6SX/i.MX8M Mini/Nano has CRC_STAT register, which contains CRC32 of the frame as it was clocked out of the DPI interface of the LCDIF. This is most likely meant as a functional safety feature. Unfortunately, there is zero documentation on how the CRC32 is calculated, there is no documentation of the polynomial, the init value, nor on which data is the checksum applied. By applying brute-force on 8 pixel / 2 line frame, which is the minimum size LCDIF would work with, it turns out the polynomial is CRC32_POLY_LE 0xedb88320 , init value is 0xffffffff , the input data are bitrev32() of the entire frame and the resulting CRC has to be also bitrev32()ed. Doing this calculation in kernel for each frame is unrealistic due to the CPU demand, so attach the CRC collected from hardware to a frame instead. The DRM subsystem already has an interface for this purpose and the CRC can be accessed e.g. via debugfs: " $ echo auto > /sys/kernel/debug/dri/1/crtc-0/crc/control $ cat /sys/kernel/debug/dri/1/crtc-0/crc/data 0x0000408c 0xa4e5cdd8 0x0000408d 0x72f537b4 " The per-frame CRC can be used by userspace e.g. during automated testing, to verify that whatever buffer was sent to be scanned out was actually scanned out of the LCDIF correctly. Acked-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexander Stein <alexander.stein@ew.tq-group.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Robby Cai <robby.cai@nxp.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Stefan Agner <stefan@agner.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20220429212313.305556-1-marex@denx.de
131 lines
4.3 KiB
C
131 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2010 Juergen Beisert, Pengutronix
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* Copyright (C) 2016 Marek Vasut <marex@denx.de>
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*
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* i.MX23/i.MX28/i.MX6SX MXSFB LCD controller driver.
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*/
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#ifndef __MXSFB_REGS_H__
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#define __MXSFB_REGS_H__
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#define REG_SET 4
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#define REG_CLR 8
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#define LCDC_CTRL 0x00
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#define LCDC_CTRL1 0x10
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#define LCDC_V3_TRANSFER_COUNT 0x20
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#define LCDC_V4_CTRL2 0x20
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#define LCDC_V4_TRANSFER_COUNT 0x30
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#define LCDC_V4_CUR_BUF 0x40
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#define LCDC_V4_NEXT_BUF 0x50
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#define LCDC_V3_CUR_BUF 0x30
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#define LCDC_V3_NEXT_BUF 0x40
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#define LCDC_VDCTRL0 0x70
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#define LCDC_VDCTRL1 0x80
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#define LCDC_VDCTRL2 0x90
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#define LCDC_VDCTRL3 0xa0
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#define LCDC_VDCTRL4 0xb0
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#define LCDC_V4_CRC_STAT 0x1a0
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#define LCDC_V4_DEBUG0 0x1d0
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#define LCDC_V3_DEBUG0 0x1f0
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#define LCDC_AS_CTRL 0x210
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#define LCDC_AS_BUF 0x220
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#define LCDC_AS_NEXT_BUF 0x230
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#define LCDC_AS_CLRKEYLOW 0x240
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#define LCDC_AS_CLRKEYHIGH 0x250
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#define CTRL_SFTRST BIT(31)
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#define CTRL_CLKGATE BIT(30)
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#define CTRL_BYPASS_COUNT BIT(19)
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#define CTRL_VSYNC_MODE BIT(18)
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#define CTRL_DOTCLK_MODE BIT(17)
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#define CTRL_DATA_SELECT BIT(16)
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#define CTRL_BUS_WIDTH_16 (0 << 10)
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#define CTRL_BUS_WIDTH_8 (1 << 10)
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#define CTRL_BUS_WIDTH_18 (2 << 10)
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#define CTRL_BUS_WIDTH_24 (3 << 10)
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#define CTRL_BUS_WIDTH_MASK (0x3 << 10)
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#define CTRL_WORD_LENGTH_16 (0 << 8)
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#define CTRL_WORD_LENGTH_8 (1 << 8)
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#define CTRL_WORD_LENGTH_18 (2 << 8)
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#define CTRL_WORD_LENGTH_24 (3 << 8)
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#define CTRL_MASTER BIT(5)
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#define CTRL_DF16 BIT(3)
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#define CTRL_DF18 BIT(2)
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#define CTRL_DF24 BIT(1)
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#define CTRL_RUN BIT(0)
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#define CTRL1_RECOVER_ON_UNDERFLOW BIT(24)
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#define CTRL1_FIFO_CLEAR BIT(21)
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#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
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#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
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#define CTRL1_CUR_FRAME_DONE_IRQ_EN BIT(13)
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#define CTRL1_CUR_FRAME_DONE_IRQ BIT(9)
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#define CTRL2_SET_OUTSTANDING_REQS_1 0
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#define CTRL2_SET_OUTSTANDING_REQS_2 (0x1 << 21)
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#define CTRL2_SET_OUTSTANDING_REQS_4 (0x2 << 21)
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#define CTRL2_SET_OUTSTANDING_REQS_8 (0x3 << 21)
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#define CTRL2_SET_OUTSTANDING_REQS_16 (0x4 << 21)
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#define CTRL2_SET_OUTSTANDING_REQS_MASK (0x7 << 21)
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#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
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#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
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#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff)
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#define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff)
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#define VDCTRL0_ENABLE_PRESENT BIT(28)
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#define VDCTRL0_VSYNC_ACT_HIGH BIT(27)
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#define VDCTRL0_HSYNC_ACT_HIGH BIT(26)
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#define VDCTRL0_DOTCLK_ACT_FALLING BIT(25)
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#define VDCTRL0_ENABLE_ACT_HIGH BIT(24)
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#define VDCTRL0_VSYNC_PERIOD_UNIT BIT(21)
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#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT BIT(20)
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#define VDCTRL0_HALF_LINE BIT(19)
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#define VDCTRL0_HALF_LINE_MODE BIT(18)
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#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
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#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
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#define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
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#define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
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#define VDCTRL3_MUX_SYNC_SIGNALS BIT(29)
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#define VDCTRL3_VSYNC_ONLY BIT(28)
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#define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16)
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#define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff)
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#define SET_VERT_WAIT_CNT(x) ((x) & 0xffff)
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#define GET_VERT_WAIT_CNT(x) ((x) & 0xffff)
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#define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */
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#define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */
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#define VDCTRL4_SYNC_SIGNALS_ON BIT(18)
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#define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff)
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#define DEBUG0_HSYNC BIT(26)
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#define DEBUG0_VSYNC BIT(25)
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#define AS_CTRL_PS_DISABLE BIT(23)
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#define AS_CTRL_ALPHA_INVERT BIT(20)
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#define AS_CTRL_ALPHA(a) (((a) & 0xff) << 8)
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#define AS_CTRL_FORMAT_RGB565 (0xe << 4)
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#define AS_CTRL_FORMAT_RGB444 (0xd << 4)
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#define AS_CTRL_FORMAT_RGB555 (0xc << 4)
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#define AS_CTRL_FORMAT_ARGB4444 (0x9 << 4)
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#define AS_CTRL_FORMAT_ARGB1555 (0x8 << 4)
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#define AS_CTRL_FORMAT_RGB888 (0x4 << 4)
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#define AS_CTRL_FORMAT_ARGB8888 (0x0 << 4)
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#define AS_CTRL_ENABLE_COLORKEY BIT(3)
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#define AS_CTRL_ALPHA_CTRL_ROP (3 << 1)
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#define AS_CTRL_ALPHA_CTRL_MULTIPLY (2 << 1)
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#define AS_CTRL_ALPHA_CTRL_OVERRIDE (1 << 1)
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#define AS_CTRL_ALPHA_CTRL_EMBEDDED (0 << 1)
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#define AS_CTRL_AS_ENABLE BIT(0)
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#define MXSFB_MIN_XRES 120
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#define MXSFB_MIN_YRES 120
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#define MXSFB_MAX_XRES 0xffff
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#define MXSFB_MAX_YRES 0xffff
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#endif /* __MXSFB_REGS_H__ */
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