f0bae243b2
-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAmZLzNIUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vwr/Q//STe2XGKI8bAKqP2wbbkzm+ISnK4A Lqf3FEAIXunxDRspszfXKKV2p4vaIkmOFiwIdtp/kWvd0DQn5+ATXJ/iQtp8aFX/ R+6BQ7EZc2G7fN5fbQuK54+CvmWEpkKEMbXYbd6ivQ14Cijdb3Nbu+w+DYFjS+6C k2a9lS1bTW7Xcy0fyiO1w6GQiWqtmOH8U3OlQtIrI0EVkDG9OG1LsLuc92/FgkOo REN+sU+hX1K5fHrvm2CtjYDn/9/B6bJ/It22H1dPgUL9nKvKC67fYzosMtUCOX1M 6XSPjZIuXOmQGeZXHhpSlVwaidxoUjYO98I7nMquxKdCy6yct3geK7ULG/xeQCgD ML7MGQB4+sTiSWalXUQaziKqF1FIDEvU3HMGXFWnoBL5l56eRp8KS1EI9Eqk9pU3 pk9fJaCkcFnkzPtMFzqPOm5q9zUZ6bGbfYb0hs72TUKplmVDhFo2T1YsW2AOyHZ7 mjuDzUYZX0H7uM1tntA56IgZX+oNOrLvhBt5L5M/BQeCsZFBBUfIcAEaYoL9LwXO AYgIG3jdqzHHyAUzutJF+XHKinJLMHm0XVYbFmO6saPhFzrUJSNHqT7NzW1DGGTl OnO8e1WNMX1EcnKvnc6fXyGmM3SgVwy45FsbG/zRnhn4uBKqKtjrh6uX/myA22LK CSeqSUK9XmXxFNA= =xjoS -----END PGP SIGNATURE----- Merge tag 'pci-v6.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull pci updates from Bjorn Helgaas: "Enumeration: - Skip E820 checks for MCFG ECAM regions for new (2016+) machines, since there's no requirement to describe them in E820 and some platforms require ECAM to work (Bjorn Helgaas) - Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more specific (Damien Le Moal) - Remove last user and pci_enable_device_io() (Heiner Kallweit) - Wait for Link Training==0 to avoid possible race (Ilpo Järvinen) - Skip waiting for devices that have been disconnected while suspended (Ilpo Järvinen) - Clear Secondary Status errors after enumeration since Master Aborts and Unsupported Request errors are an expected part of enumeration (Vidya Sagar) MSI: - Remove unused IMS (Interrupt Message Store) support (Bjorn Helgaas) Error handling: - Mask Genesys GL975x SD host controller Replay Timer Timeout correctable errors caused by a hardware defect; the errors cause interrupts that prevent system suspend (Kai-Heng Feng) - Fix EDR-related _DSM support, which previously evaluated revision 5 but assumed revision 6 behavior (Kuppuswamy Sathyanarayanan) ASPM: - Simplify link state definitions and mask calculation (Ilpo Järvinen) Power management: - Avoid D3cold for HP Pavilion 17 PC/1972 PCIe Ports, where BIOS apparently doesn't know how to put them back in D0 (Mario Limonciello) CXL: - Support resetting CXL devices; special handling required because CXL Ports mask Secondary Bus Reset by default (Dave Jiang) DOE: - Support DOE Discovery Version 2 (Alexey Kardashevskiy) Endpoint framework: - Set endpoint BAR to be 64-bit if the driver says that's all the device supports, in addition to doing so if the size is >2GB (Niklas Cassel) - Simplify endpoint BAR allocation and setting interfaces (Niklas Cassel) Cadence PCIe controller driver: - Drop DT binding redundant msi-parent and pci-bus.yaml (Krzysztof Kozlowski) Cadence PCIe endpoint driver: - Configure endpoint BARs to be 64-bit based on the BAR type, not the BAR value (Niklas Cassel) Freescale Layerscape PCIe controller driver: - Convert DT binding to YAML (Frank Li) MediaTek MT7621 PCIe controller driver: - Add DT binding missing 'reg' property for child Root Ports (Krzysztof Kozlowski) - Fix theoretical string truncation in PHY name (Sergio Paracuellos) NVIDIA Tegra194 PCIe controller driver: - Return success for endpoint probe instead of falling through to the failure path (Vidya Sagar) Renesas R-Car PCIe controller driver: - Add DT binding missing IOMMU properties (Geert Uytterhoeven) - Add DT binding R-Car V4H compatible for host and endpoint mode (Yoshihiro Shimoda) Rockchip PCIe controller driver: - Configure endpoint BARs to be 64-bit based on the BAR type, not the BAR value (Niklas Cassel) - Add DT binding missing maxItems to ep-gpios (Krzysztof Kozlowski) - Set the Subsystem Vendor ID, which was previously zero because it was masked incorrectly (Rick Wertenbroek) Synopsys DesignWare PCIe controller driver: - Restructure DBI register access to accommodate devices where this requires Refclk to be active (Manivannan Sadhasivam) - Remove the deinit() callback, which was only need by the pcie-rcar-gen4, and do it directly in that driver (Manivannan Sadhasivam) - Add dw_pcie_ep_cleanup() so drivers that support PERST# can clean up things like eDMA (Manivannan Sadhasivam) - Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit() to make it parallel to dw_pcie_ep_init() (Manivannan Sadhasivam) - Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers() to reflect the actual functionality (Manivannan Sadhasivam) - Call dw_pcie_ep_init_registers() directly from all the glue drivers, not just those that require active Refclk from the host (Manivannan Sadhasivam) - Remove the "core_init_notifier" flag, which was an obscure way for glue drivers to indicate that they depend on Refclk from the host (Manivannan Sadhasivam) TI J721E PCIe driver: - Add DT binding J784S4 SoC Device ID (Siddharth Vadapalli) - Add DT binding J722S SoC support (Siddharth Vadapalli) TI Keystone PCIe controller driver: - Add DT binding missing num-viewport, phys and phy-name properties (Jan Kiszka) Miscellaneous: - Constify and annotate with __ro_after_init (Heiner Kallweit) - Convert DT bindings to YAML (Krzysztof Kozlowski) - Check for kcalloc() failure in of_pci_prop_intr_map() (Duoming Zhou)" * tag 'pci-v6.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (97 commits) PCI: Do not wait for disconnected devices when resuming x86/pci: Skip early E820 check for ECAM region PCI: Remove unused pci_enable_device_io() ata: pata_cs5520: Remove unnecessary call to pci_enable_device_io() PCI: Update pci_find_capability() stub return types PCI: Remove PCI_IRQ_LEGACY scsi: vmw_pvscsi: Do not use PCI_IRQ_LEGACY instead of PCI_IRQ_LEGACY scsi: pmcraid: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: mpt3sas: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: megaraid_sas: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: ipr: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: hpsa: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: arcmsr: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY wifi: rtw89: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY dt-bindings: PCI: rockchip,rk3399-pcie: Add missing maxItems to ep-gpios Revert "genirq/msi: Provide constants for PCI/IMS support" Revert "x86/apic/msi: Enable PCI/IMS" Revert "iommu/vt-d: Enable PCI/IMS" Revert "iommu/amd: Enable PCI/IMS" Revert "PCI/MSI: Provide IMS (Interrupt Message Store) support" ...
581 lines
15 KiB
C
581 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2020 Intel Corporation. */
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <cxlmem.h>
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#include <cxlpci.h>
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#include <pmu.h>
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#include "core.h"
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/**
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* DOC: cxl registers
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*
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* CXL device capabilities are enumerated by PCI DVSEC (Designated
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* Vendor-specific) and / or descriptors provided by platform firmware.
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* They can be defined as a set like the device and component registers
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* mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and
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* Extended Capabilities, or they can be individual capabilities
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* appended to bridged and endpoint devices.
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*
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* Provide common infrastructure for enumerating and mapping these
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* discrete capabilities.
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*/
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/**
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* cxl_probe_component_regs() - Detect CXL Component register blocks
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* @dev: Host device of the @base mapping
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* @base: Mapping containing the HDM Decoder Capability Header
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* @map: Map object describing the register block information found
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*
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* See CXL 2.0 8.2.4 Component Register Layout and Definition
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* See CXL 2.0 8.2.5.5 CXL Device Register Interface
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*
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* Probe for component register information and return it in map object.
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*/
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void cxl_probe_component_regs(struct device *dev, void __iomem *base,
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struct cxl_component_reg_map *map)
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{
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int cap, cap_count;
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u32 cap_array;
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*map = (struct cxl_component_reg_map) { 0 };
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/*
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* CXL.cache and CXL.mem registers are at offset 0x1000 as defined in
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* CXL 2.0 8.2.4 Table 141.
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*/
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base += CXL_CM_OFFSET;
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cap_array = readl(base + CXL_CM_CAP_HDR_OFFSET);
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if (FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, cap_array) != CM_CAP_HDR_CAP_ID) {
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dev_err(dev,
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"Couldn't locate the CXL.cache and CXL.mem capability array header.\n");
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return;
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}
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/* It's assumed that future versions will be backward compatible */
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cap_count = FIELD_GET(CXL_CM_CAP_HDR_ARRAY_SIZE_MASK, cap_array);
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for (cap = 1; cap <= cap_count; cap++) {
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void __iomem *register_block;
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struct cxl_reg_map *rmap;
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u16 cap_id, offset;
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u32 length, hdr;
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hdr = readl(base + cap * 0x4);
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cap_id = FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, hdr);
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offset = FIELD_GET(CXL_CM_CAP_PTR_MASK, hdr);
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register_block = base + offset;
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hdr = readl(register_block);
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rmap = NULL;
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switch (cap_id) {
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case CXL_CM_CAP_CAP_ID_HDM: {
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int decoder_cnt;
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dev_dbg(dev, "found HDM decoder capability (0x%x)\n",
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offset);
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decoder_cnt = cxl_hdm_decoder_count(hdr);
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length = 0x20 * decoder_cnt + 0x10;
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rmap = &map->hdm_decoder;
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break;
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}
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case CXL_CM_CAP_CAP_ID_RAS:
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dev_dbg(dev, "found RAS capability (0x%x)\n",
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offset);
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length = CXL_RAS_CAPABILITY_LENGTH;
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rmap = &map->ras;
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break;
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default:
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dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id,
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offset);
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break;
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}
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if (!rmap)
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continue;
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rmap->valid = true;
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rmap->id = cap_id;
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rmap->offset = CXL_CM_OFFSET + offset;
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rmap->size = length;
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}
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}
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EXPORT_SYMBOL_NS_GPL(cxl_probe_component_regs, CXL);
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/**
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* cxl_probe_device_regs() - Detect CXL Device register blocks
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* @dev: Host device of the @base mapping
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* @base: Mapping of CXL 2.0 8.2.8 CXL Device Register Interface
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* @map: Map object describing the register block information found
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*
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* Probe for device register information and return it in map object.
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*/
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void cxl_probe_device_regs(struct device *dev, void __iomem *base,
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struct cxl_device_reg_map *map)
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{
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int cap, cap_count;
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u64 cap_array;
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*map = (struct cxl_device_reg_map){ 0 };
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cap_array = readq(base + CXLDEV_CAP_ARRAY_OFFSET);
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if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) !=
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CXLDEV_CAP_ARRAY_CAP_ID)
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return;
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cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array);
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for (cap = 1; cap <= cap_count; cap++) {
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struct cxl_reg_map *rmap;
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u32 offset, length;
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u16 cap_id;
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cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK,
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readl(base + cap * 0x10));
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offset = readl(base + cap * 0x10 + 0x4);
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length = readl(base + cap * 0x10 + 0x8);
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rmap = NULL;
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switch (cap_id) {
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case CXLDEV_CAP_CAP_ID_DEVICE_STATUS:
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dev_dbg(dev, "found Status capability (0x%x)\n", offset);
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rmap = &map->status;
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break;
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case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX:
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dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset);
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rmap = &map->mbox;
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break;
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case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX:
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dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset);
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break;
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case CXLDEV_CAP_CAP_ID_MEMDEV:
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dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset);
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rmap = &map->memdev;
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break;
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default:
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if (cap_id >= 0x8000)
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dev_dbg(dev, "Vendor cap ID: %#x offset: %#x\n", cap_id, offset);
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else
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dev_dbg(dev, "Unknown cap ID: %#x offset: %#x\n", cap_id, offset);
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break;
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}
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if (!rmap)
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continue;
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rmap->valid = true;
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rmap->id = cap_id;
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rmap->offset = offset;
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rmap->size = length;
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}
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}
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EXPORT_SYMBOL_NS_GPL(cxl_probe_device_regs, CXL);
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void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
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resource_size_t length)
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{
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void __iomem *ret_val;
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struct resource *res;
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if (WARN_ON_ONCE(addr == CXL_RESOURCE_NONE))
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return NULL;
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res = devm_request_mem_region(dev, addr, length, dev_name(dev));
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if (!res) {
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resource_size_t end = addr + length - 1;
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dev_err(dev, "Failed to request region %pa-%pa\n", &addr, &end);
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return NULL;
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}
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ret_val = devm_ioremap(dev, addr, length);
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if (!ret_val)
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dev_err(dev, "Failed to map region %pr\n", res);
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return ret_val;
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}
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int cxl_map_component_regs(const struct cxl_register_map *map,
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struct cxl_component_regs *regs,
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unsigned long map_mask)
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{
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struct device *host = map->host;
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struct mapinfo {
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const struct cxl_reg_map *rmap;
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void __iomem **addr;
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} mapinfo[] = {
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{ &map->component_map.hdm_decoder, ®s->hdm_decoder },
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{ &map->component_map.ras, ®s->ras },
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(mapinfo); i++) {
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struct mapinfo *mi = &mapinfo[i];
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resource_size_t addr;
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resource_size_t length;
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if (!mi->rmap->valid)
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continue;
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if (!test_bit(mi->rmap->id, &map_mask))
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continue;
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addr = map->resource + mi->rmap->offset;
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length = mi->rmap->size;
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*(mi->addr) = devm_cxl_iomap_block(host, addr, length);
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if (!*(mi->addr))
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return -ENOMEM;
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}
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL);
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int cxl_map_device_regs(const struct cxl_register_map *map,
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struct cxl_device_regs *regs)
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{
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struct device *host = map->host;
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resource_size_t phys_addr = map->resource;
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struct mapinfo {
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const struct cxl_reg_map *rmap;
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void __iomem **addr;
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} mapinfo[] = {
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{ &map->device_map.status, ®s->status, },
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{ &map->device_map.mbox, ®s->mbox, },
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{ &map->device_map.memdev, ®s->memdev, },
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(mapinfo); i++) {
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struct mapinfo *mi = &mapinfo[i];
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resource_size_t length;
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resource_size_t addr;
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if (!mi->rmap->valid)
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continue;
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addr = phys_addr + mi->rmap->offset;
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length = mi->rmap->size;
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*(mi->addr) = devm_cxl_iomap_block(host, addr, length);
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if (!*(mi->addr))
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return -ENOMEM;
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}
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_map_device_regs, CXL);
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static bool cxl_decode_regblock(struct pci_dev *pdev, u32 reg_lo, u32 reg_hi,
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struct cxl_register_map *map)
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{
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u8 reg_type = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo);
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int bar = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BIR_MASK, reg_lo);
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u64 offset = ((u64)reg_hi << 32) |
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(reg_lo & CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK);
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if (offset > pci_resource_len(pdev, bar)) {
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dev_warn(&pdev->dev,
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"BAR%d: %pr: too small (offset: %pa, type: %d)\n", bar,
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&pdev->resource[bar], &offset, reg_type);
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return false;
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}
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map->reg_type = reg_type;
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map->resource = pci_resource_start(pdev, bar) + offset;
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map->max_size = pci_resource_len(pdev, bar) - offset;
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return true;
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}
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/**
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* cxl_find_regblock_instance() - Locate a register block by type / index
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* @pdev: The CXL PCI device to enumerate.
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* @type: Register Block Indicator id
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* @map: Enumeration output, clobbered on error
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* @index: Index into which particular instance of a regblock wanted in the
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* order found in register locator DVSEC.
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*
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* Return: 0 if register block enumerated, negative error code otherwise
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*
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* A CXL DVSEC may point to one or more register blocks, search for them
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* by @type and @index.
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*/
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int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
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struct cxl_register_map *map, int index)
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{
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u32 regloc_size, regblocks;
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int instance = 0;
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int regloc, i;
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*map = (struct cxl_register_map) {
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.host = &pdev->dev,
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.resource = CXL_RESOURCE_NONE,
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};
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regloc = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
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CXL_DVSEC_REG_LOCATOR);
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if (!regloc)
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return -ENXIO;
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pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size);
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regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size);
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regloc += CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET;
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regblocks = (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8;
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for (i = 0; i < regblocks; i++, regloc += 8) {
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u32 reg_lo, reg_hi;
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pci_read_config_dword(pdev, regloc, ®_lo);
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pci_read_config_dword(pdev, regloc + 4, ®_hi);
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if (!cxl_decode_regblock(pdev, reg_lo, reg_hi, map))
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continue;
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if (map->reg_type == type) {
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if (index == instance)
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return 0;
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instance++;
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}
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}
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map->resource = CXL_RESOURCE_NONE;
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return -ENODEV;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_find_regblock_instance, CXL);
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/**
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* cxl_find_regblock() - Locate register blocks by type
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* @pdev: The CXL PCI device to enumerate.
|
|
* @type: Register Block Indicator id
|
|
* @map: Enumeration output, clobbered on error
|
|
*
|
|
* Return: 0 if register block enumerated, negative error code otherwise
|
|
*
|
|
* A CXL DVSEC may point to one or more register blocks, search for them
|
|
* by @type.
|
|
*/
|
|
int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
|
|
struct cxl_register_map *map)
|
|
{
|
|
return cxl_find_regblock_instance(pdev, type, map, 0);
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
|
|
|
|
/**
|
|
* cxl_count_regblock() - Count instances of a given regblock type.
|
|
* @pdev: The CXL PCI device to enumerate.
|
|
* @type: Register Block Indicator id
|
|
*
|
|
* Some regblocks may be repeated. Count how many instances.
|
|
*
|
|
* Return: count of matching regblocks.
|
|
*/
|
|
int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)
|
|
{
|
|
struct cxl_register_map map;
|
|
int rc, count = 0;
|
|
|
|
while (1) {
|
|
rc = cxl_find_regblock_instance(pdev, type, &map, count);
|
|
if (rc)
|
|
return count;
|
|
count++;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
|
|
|
|
int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs)
|
|
{
|
|
struct device *dev = map->host;
|
|
resource_size_t phys_addr;
|
|
|
|
phys_addr = map->resource;
|
|
regs->pmu = devm_cxl_iomap_block(dev, phys_addr, CXL_PMU_REGMAP_SIZE);
|
|
if (!regs->pmu)
|
|
return -ENOMEM;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(cxl_map_pmu_regs, CXL);
|
|
|
|
static int cxl_map_regblock(struct cxl_register_map *map)
|
|
{
|
|
struct device *host = map->host;
|
|
|
|
map->base = ioremap(map->resource, map->max_size);
|
|
if (!map->base) {
|
|
dev_err(host, "failed to map registers\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dev_dbg(host, "Mapped CXL Memory Device resource %pa\n", &map->resource);
|
|
return 0;
|
|
}
|
|
|
|
static void cxl_unmap_regblock(struct cxl_register_map *map)
|
|
{
|
|
iounmap(map->base);
|
|
map->base = NULL;
|
|
}
|
|
|
|
static int cxl_probe_regs(struct cxl_register_map *map)
|
|
{
|
|
struct cxl_component_reg_map *comp_map;
|
|
struct cxl_device_reg_map *dev_map;
|
|
struct device *host = map->host;
|
|
void __iomem *base = map->base;
|
|
|
|
switch (map->reg_type) {
|
|
case CXL_REGLOC_RBI_COMPONENT:
|
|
comp_map = &map->component_map;
|
|
cxl_probe_component_regs(host, base, comp_map);
|
|
dev_dbg(host, "Set up component registers\n");
|
|
break;
|
|
case CXL_REGLOC_RBI_MEMDEV:
|
|
dev_map = &map->device_map;
|
|
cxl_probe_device_regs(host, base, dev_map);
|
|
if (!dev_map->status.valid || !dev_map->mbox.valid ||
|
|
!dev_map->memdev.valid) {
|
|
dev_err(host, "registers not found: %s%s%s\n",
|
|
!dev_map->status.valid ? "status " : "",
|
|
!dev_map->mbox.valid ? "mbox " : "",
|
|
!dev_map->memdev.valid ? "memdev " : "");
|
|
return -ENXIO;
|
|
}
|
|
|
|
dev_dbg(host, "Probing device registers...\n");
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cxl_setup_regs(struct cxl_register_map *map)
|
|
{
|
|
int rc;
|
|
|
|
rc = cxl_map_regblock(map);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = cxl_probe_regs(map);
|
|
cxl_unmap_regblock(map);
|
|
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, CXL);
|
|
|
|
u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb)
|
|
{
|
|
void __iomem *addr;
|
|
u16 offset = 0;
|
|
u32 cap_hdr;
|
|
|
|
if (WARN_ON_ONCE(rcrb == CXL_RESOURCE_NONE))
|
|
return 0;
|
|
|
|
if (!request_mem_region(rcrb, SZ_4K, dev_name(dev)))
|
|
return 0;
|
|
|
|
addr = ioremap(rcrb, SZ_4K);
|
|
if (!addr)
|
|
goto out;
|
|
|
|
cap_hdr = readl(addr + offset);
|
|
while (PCI_EXT_CAP_ID(cap_hdr) != PCI_EXT_CAP_ID_ERR) {
|
|
offset = PCI_EXT_CAP_NEXT(cap_hdr);
|
|
|
|
/* Offset 0 terminates capability list. */
|
|
if (!offset)
|
|
break;
|
|
cap_hdr = readl(addr + offset);
|
|
}
|
|
|
|
if (offset)
|
|
dev_dbg(dev, "found AER extended capability (0x%x)\n", offset);
|
|
|
|
iounmap(addr);
|
|
out:
|
|
release_mem_region(rcrb, SZ_4K);
|
|
|
|
return offset;
|
|
}
|
|
|
|
resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri,
|
|
enum cxl_rcrb which)
|
|
{
|
|
resource_size_t component_reg_phys;
|
|
resource_size_t rcrb = ri->base;
|
|
void __iomem *addr;
|
|
u32 bar0, bar1;
|
|
u16 cmd;
|
|
u32 id;
|
|
|
|
if (which == CXL_RCRB_UPSTREAM)
|
|
rcrb += SZ_4K;
|
|
|
|
/*
|
|
* RCRB's BAR[0..1] point to component block containing CXL
|
|
* subsystem component registers. MEMBAR extraction follows
|
|
* the PCI Base spec here, esp. 64 bit extraction and memory
|
|
* ranges alignment (6.0, 7.5.1.2.1).
|
|
*/
|
|
if (!request_mem_region(rcrb, SZ_4K, "CXL RCRB"))
|
|
return CXL_RESOURCE_NONE;
|
|
addr = ioremap(rcrb, SZ_4K);
|
|
if (!addr) {
|
|
dev_err(dev, "Failed to map region %pr\n", addr);
|
|
release_mem_region(rcrb, SZ_4K);
|
|
return CXL_RESOURCE_NONE;
|
|
}
|
|
|
|
id = readl(addr + PCI_VENDOR_ID);
|
|
cmd = readw(addr + PCI_COMMAND);
|
|
bar0 = readl(addr + PCI_BASE_ADDRESS_0);
|
|
bar1 = readl(addr + PCI_BASE_ADDRESS_1);
|
|
iounmap(addr);
|
|
release_mem_region(rcrb, SZ_4K);
|
|
|
|
/*
|
|
* Sanity check, see CXL 3.0 Figure 9-8 CXL Device that Does Not
|
|
* Remap Upstream Port and Component Registers
|
|
*/
|
|
if (id == U32_MAX) {
|
|
if (which == CXL_RCRB_DOWNSTREAM)
|
|
dev_err(dev, "Failed to access Downstream Port RCRB\n");
|
|
return CXL_RESOURCE_NONE;
|
|
}
|
|
if (!(cmd & PCI_COMMAND_MEMORY))
|
|
return CXL_RESOURCE_NONE;
|
|
/* The RCRB is a Memory Window, and the MEM_TYPE_1M bit is obsolete */
|
|
if (bar0 & (PCI_BASE_ADDRESS_MEM_TYPE_1M | PCI_BASE_ADDRESS_SPACE_IO))
|
|
return CXL_RESOURCE_NONE;
|
|
|
|
component_reg_phys = bar0 & PCI_BASE_ADDRESS_MEM_MASK;
|
|
if (bar0 & PCI_BASE_ADDRESS_MEM_TYPE_64)
|
|
component_reg_phys |= ((u64)bar1) << 32;
|
|
|
|
if (!component_reg_phys)
|
|
return CXL_RESOURCE_NONE;
|
|
|
|
/* MEMBAR is block size (64k) aligned. */
|
|
if (!IS_ALIGNED(component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE))
|
|
return CXL_RESOURCE_NONE;
|
|
|
|
return component_reg_phys;
|
|
}
|
|
|
|
resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
|
|
struct cxl_dport *dport)
|
|
{
|
|
if (!dport->rch)
|
|
return CXL_RESOURCE_NONE;
|
|
return __rcrb_to_component(dev, &dport->rcrb, CXL_RCRB_UPSTREAM);
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(cxl_rcd_component_reg_phys, CXL);
|