5647847556
Series to fix XOR math for DPA to SPA translation - Refactor and fold cxl_trace_hpa() into cxl_dpa_to_hpa() - Complete DPA->HPA->SPA translation and correct XOR translation issue - Add new method to verify a CXL target position - Remove old method of CXL target position verifiation
932 lines
23 KiB
C
932 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include <linux/node.h>
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#include <asm/div64.h>
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#include "cxlpci.h"
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#include "cxl.h"
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#define CXL_RCRB_SIZE SZ_8K
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struct cxl_cxims_data {
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int nr_maps;
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u64 xormaps[] __counted_by(nr_maps);
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};
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static const guid_t acpi_cxl_qtg_id_guid =
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GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
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0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
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static u64 cxl_xor_hpa_to_spa(struct cxl_root_decoder *cxlrd, u64 hpa)
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{
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struct cxl_cxims_data *cximsd = cxlrd->platform_data;
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int hbiw = cxlrd->cxlsd.nr_targets;
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u64 val;
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int pos;
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/* No xormaps for host bridge interleave ways of 1 or 3 */
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if (hbiw == 1 || hbiw == 3)
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return hpa;
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/*
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* For root decoders using xormaps (hbiw: 2,4,6,8,12,16) restore
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* the position bit to its value before the xormap was applied at
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* HPA->DPA translation.
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*
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* pos is the lowest set bit in an XORMAP
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* val is the XORALLBITS(HPA & XORMAP)
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*
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* XORALLBITS: The CXL spec (3.1 Table 9-22) defines XORALLBITS
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* as an operation that outputs a single bit by XORing all the
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* bits in the input (hpa & xormap). Implement XORALLBITS using
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* hweight64(). If the hamming weight is even the XOR of those
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* bits results in val==0, if odd the XOR result is val==1.
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*/
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for (int i = 0; i < cximsd->nr_maps; i++) {
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if (!cximsd->xormaps[i])
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continue;
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pos = __ffs(cximsd->xormaps[i]);
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val = (hweight64(hpa & cximsd->xormaps[i]) & 1);
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hpa = (hpa & ~(1ULL << pos)) | (val << pos);
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}
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return hpa;
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}
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struct cxl_cxims_context {
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struct device *dev;
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struct cxl_root_decoder *cxlrd;
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};
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static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
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struct cxl_cxims_context *ctx = arg;
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struct cxl_root_decoder *cxlrd = ctx->cxlrd;
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struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
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struct device *dev = ctx->dev;
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struct cxl_cxims_data *cximsd;
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unsigned int hbig, nr_maps;
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int rc;
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rc = eig_to_granularity(cxims->hbig, &hbig);
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if (rc)
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return rc;
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/* Does this CXIMS entry apply to the given CXL Window? */
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if (hbig != cxld->interleave_granularity)
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return 0;
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/* IW 1,3 do not use xormaps and skip this parsing entirely */
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if (is_power_of_2(cxld->interleave_ways))
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/* 2, 4, 8, 16 way */
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nr_maps = ilog2(cxld->interleave_ways);
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else
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/* 6, 12 way */
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nr_maps = ilog2(cxld->interleave_ways / 3);
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if (cxims->nr_xormaps < nr_maps) {
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dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
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cxims->nr_xormaps, nr_maps);
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return -ENXIO;
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}
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cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),
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GFP_KERNEL);
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if (!cximsd)
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return -ENOMEM;
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cximsd->nr_maps = nr_maps;
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memcpy(cximsd->xormaps, cxims->xormap_list,
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nr_maps * sizeof(*cximsd->xormaps));
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cxlrd->platform_data = cximsd;
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return 0;
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}
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static unsigned long cfmws_to_decoder_flags(int restrictions)
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{
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unsigned long flags = CXL_DECODER_F_ENABLE;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
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flags |= CXL_DECODER_F_TYPE2;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
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flags |= CXL_DECODER_F_TYPE3;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
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flags |= CXL_DECODER_F_RAM;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
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flags |= CXL_DECODER_F_PMEM;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
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flags |= CXL_DECODER_F_LOCK;
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return flags;
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}
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static int cxl_acpi_cfmws_verify(struct device *dev,
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struct acpi_cedt_cfmws *cfmws)
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{
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int rc, expected_len;
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unsigned int ways;
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if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&
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cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
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dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",
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cfmws->interleave_arithmetic);
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return -EINVAL;
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}
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if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
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dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
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return -EINVAL;
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}
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if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
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dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
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return -EINVAL;
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}
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rc = eiw_to_ways(cfmws->interleave_ways, &ways);
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if (rc) {
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dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
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cfmws->interleave_ways);
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return -EINVAL;
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}
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expected_len = struct_size(cfmws, interleave_targets, ways);
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if (cfmws->header.length < expected_len) {
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dev_err(dev, "CFMWS length %d less than expected %d\n",
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cfmws->header.length, expected_len);
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return -EINVAL;
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}
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if (cfmws->header.length > expected_len)
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dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
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cfmws->header.length, expected_len);
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return 0;
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}
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/*
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* Note, @dev must be the first member, see 'struct cxl_chbs_context'
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* and mock_acpi_table_parse_cedt()
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*/
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struct cxl_cfmws_context {
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struct device *dev;
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struct cxl_port *root_port;
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struct resource *cxl_res;
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int id;
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};
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/**
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* cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM
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* @handle: ACPI handle
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* @coord: performance access coordinates
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* @entries: number of QTG IDs to return
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* @qos_class: int array provided by caller to return QTG IDs
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*
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* Return: number of QTG IDs returned, or -errno for errors
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*
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* Issue QTG _DSM with accompanied bandwidth and latency data in order to get
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* the QTG IDs that are suitable for the performance point in order of most
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* suitable to least suitable. Write back array of QTG IDs and return the
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* actual number of QTG IDs written back.
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*/
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static int
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cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,
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int entries, int *qos_class)
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{
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union acpi_object *out_obj, *out_buf, *obj;
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union acpi_object in_array[4] = {
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[0].integer = { ACPI_TYPE_INTEGER, coord->read_latency },
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[1].integer = { ACPI_TYPE_INTEGER, coord->write_latency },
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[2].integer = { ACPI_TYPE_INTEGER, coord->read_bandwidth },
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[3].integer = { ACPI_TYPE_INTEGER, coord->write_bandwidth },
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};
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union acpi_object in_obj = {
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.package = {
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.type = ACPI_TYPE_PACKAGE,
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.count = 4,
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.elements = in_array,
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},
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};
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int count, pkg_entries, i;
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u16 max_qtg;
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int rc;
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if (!entries)
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return -EINVAL;
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out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);
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if (!out_obj)
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return -ENXIO;
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if (out_obj->type != ACPI_TYPE_PACKAGE) {
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rc = -ENXIO;
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goto out;
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}
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/* Check Max QTG ID */
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obj = &out_obj->package.elements[0];
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if (obj->type != ACPI_TYPE_INTEGER) {
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rc = -ENXIO;
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goto out;
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}
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max_qtg = obj->integer.value;
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/* It's legal to have 0 QTG entries */
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pkg_entries = out_obj->package.count;
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if (pkg_entries <= 1) {
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rc = 0;
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goto out;
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}
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/* Retrieve QTG IDs package */
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obj = &out_obj->package.elements[1];
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if (obj->type != ACPI_TYPE_PACKAGE) {
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rc = -ENXIO;
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goto out;
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}
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pkg_entries = obj->package.count;
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count = min(entries, pkg_entries);
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for (i = 0; i < count; i++) {
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u16 qtg_id;
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out_buf = &obj->package.elements[i];
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if (out_buf->type != ACPI_TYPE_INTEGER) {
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rc = -ENXIO;
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goto out;
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}
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qtg_id = out_buf->integer.value;
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if (qtg_id > max_qtg)
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pr_warn("QTG ID %u greater than MAX %u\n",
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qtg_id, max_qtg);
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qos_class[i] = qtg_id;
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}
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rc = count;
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out:
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ACPI_FREE(out_obj);
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return rc;
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}
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static int cxl_acpi_qos_class(struct cxl_root *cxl_root,
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struct access_coordinate *coord, int entries,
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int *qos_class)
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{
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struct device *dev = cxl_root->port.uport_dev;
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acpi_handle handle;
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if (!dev_is_platform(dev))
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return -ENODEV;
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handle = ACPI_HANDLE(dev);
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if (!handle)
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return -ENODEV;
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return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);
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}
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static const struct cxl_root_ops acpi_root_ops = {
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.qos_class = cxl_acpi_qos_class,
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};
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static void del_cxl_resource(struct resource *res)
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{
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if (!res)
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return;
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kfree(res->name);
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kfree(res);
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}
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static struct resource *alloc_cxl_resource(resource_size_t base,
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resource_size_t n, int id)
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{
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struct resource *res __free(kfree) = kzalloc(sizeof(*res), GFP_KERNEL);
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if (!res)
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return NULL;
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res->start = base;
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res->end = base + n - 1;
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res->flags = IORESOURCE_MEM;
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res->name = kasprintf(GFP_KERNEL, "CXL Window %d", id);
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if (!res->name)
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return NULL;
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return no_free_ptr(res);
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}
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static int add_or_reset_cxl_resource(struct resource *parent, struct resource *res)
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{
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int rc = insert_resource(parent, res);
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if (rc)
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del_cxl_resource(res);
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return rc;
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}
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DEFINE_FREE(put_cxlrd, struct cxl_root_decoder *,
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if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev))
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DEFINE_FREE(del_cxl_resource, struct resource *, if (_T) del_cxl_resource(_T))
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static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws,
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struct cxl_cfmws_context *ctx)
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{
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int target_map[CXL_DECODER_MAX_INTERLEAVE];
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struct cxl_port *root_port = ctx->root_port;
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struct cxl_cxims_context cxims_ctx;
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struct device *dev = ctx->dev;
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struct cxl_decoder *cxld;
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unsigned int ways, i, ig;
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int rc;
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rc = cxl_acpi_cfmws_verify(dev, cfmws);
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if (rc)
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return rc;
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rc = eiw_to_ways(cfmws->interleave_ways, &ways);
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if (rc)
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return rc;
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rc = eig_to_granularity(cfmws->granularity, &ig);
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if (rc)
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return rc;
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for (i = 0; i < ways; i++)
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target_map[i] = cfmws->interleave_targets[i];
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struct resource *res __free(del_cxl_resource) = alloc_cxl_resource(
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cfmws->base_hpa, cfmws->window_size, ctx->id++);
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if (!res)
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return -ENOMEM;
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/* add to the local resource tracking to establish a sort order */
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rc = add_or_reset_cxl_resource(ctx->cxl_res, no_free_ptr(res));
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if (rc)
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return rc;
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struct cxl_root_decoder *cxlrd __free(put_cxlrd) =
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cxl_root_decoder_alloc(root_port, ways);
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if (IS_ERR(cxlrd))
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return PTR_ERR(cxlrd);
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cxld = &cxlrd->cxlsd.cxld;
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cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
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cxld->target_type = CXL_DECODER_HOSTONLYMEM;
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cxld->hpa_range = (struct range) {
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.start = cfmws->base_hpa,
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.end = cfmws->base_hpa + cfmws->window_size - 1,
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};
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cxld->interleave_ways = ways;
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/*
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* Minimize the x1 granularity to advertise support for any
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* valid region granularity
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*/
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if (ways == 1)
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ig = CXL_DECODER_MIN_GRANULARITY;
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cxld->interleave_granularity = ig;
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if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
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if (ways != 1 && ways != 3) {
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cxims_ctx = (struct cxl_cxims_context) {
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.dev = dev,
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.cxlrd = cxlrd,
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};
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rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
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cxl_parse_cxims, &cxims_ctx);
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if (rc < 0)
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return rc;
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if (!cxlrd->platform_data) {
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dev_err(dev, "No CXIMS for HBIG %u\n", ig);
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return -EINVAL;
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}
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}
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}
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cxlrd->qos_class = cfmws->qtg_id;
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if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR)
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cxlrd->hpa_to_spa = cxl_xor_hpa_to_spa;
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rc = cxl_decoder_add(cxld, target_map);
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if (rc)
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return rc;
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return cxl_root_decoder_autoremove(dev, no_free_ptr(cxlrd));
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}
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static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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struct acpi_cedt_cfmws *cfmws = (struct acpi_cedt_cfmws *)header;
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struct cxl_cfmws_context *ctx = arg;
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struct device *dev = ctx->dev;
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int rc;
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rc = __cxl_parse_cfmws(cfmws, ctx);
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if (rc)
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dev_err(dev,
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"Failed to add decode range: [%#llx - %#llx] (%d)\n",
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cfmws->base_hpa,
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cfmws->base_hpa + cfmws->window_size - 1, rc);
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else
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dev_dbg(dev, "decode range: node: %d range [%#llx - %#llx]\n",
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phys_to_target_node(cfmws->base_hpa), cfmws->base_hpa,
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cfmws->base_hpa + cfmws->window_size - 1);
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/* never fail cxl_acpi load for a single window failure */
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return 0;
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}
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__mock struct acpi_device *to_cxl_host_bridge(struct device *host,
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struct device *dev)
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{
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struct acpi_device *adev = to_acpi_device(dev);
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if (!acpi_pci_find_root(adev->handle))
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return NULL;
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if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
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return adev;
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return NULL;
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}
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/* Note, @dev is used by mock_acpi_table_parse_cedt() */
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struct cxl_chbs_context {
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struct device *dev;
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unsigned long long uid;
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resource_size_t base;
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u32 cxl_version;
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int nr_versions;
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u32 saved_version;
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};
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static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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struct cxl_chbs_context *ctx = arg;
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struct acpi_cedt_chbs *chbs;
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chbs = (struct acpi_cedt_chbs *) header;
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|
|
|
if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&
|
|
chbs->length != CXL_RCRB_SIZE)
|
|
return 0;
|
|
|
|
if (!chbs->base)
|
|
return 0;
|
|
|
|
if (ctx->saved_version != chbs->cxl_version) {
|
|
/*
|
|
* cxl_version cannot be overwritten before the next two
|
|
* checks, then use saved_version
|
|
*/
|
|
ctx->saved_version = chbs->cxl_version;
|
|
ctx->nr_versions++;
|
|
}
|
|
|
|
if (ctx->base != CXL_RESOURCE_NONE)
|
|
return 0;
|
|
|
|
if (ctx->uid != chbs->uid)
|
|
return 0;
|
|
|
|
ctx->cxl_version = chbs->cxl_version;
|
|
ctx->base = chbs->base;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,
|
|
struct cxl_chbs_context *ctx)
|
|
{
|
|
unsigned long long uid;
|
|
int rc;
|
|
|
|
rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);
|
|
if (rc != AE_OK) {
|
|
dev_err(dev, "unable to retrieve _UID\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
dev_dbg(dev, "UID found: %lld\n", uid);
|
|
*ctx = (struct cxl_chbs_context) {
|
|
.dev = dev,
|
|
.uid = uid,
|
|
.base = CXL_RESOURCE_NONE,
|
|
.cxl_version = UINT_MAX,
|
|
.saved_version = UINT_MAX,
|
|
};
|
|
|
|
acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx);
|
|
|
|
if (ctx->nr_versions > 1) {
|
|
/*
|
|
* Disclaim eRCD support given some component register may
|
|
* only be found via CHBCR
|
|
*/
|
|
dev_info(dev, "Unsupported platform config, mixed Virtual Host and Restricted CXL Host hierarchy.");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)
|
|
{
|
|
struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);
|
|
u32 uid;
|
|
|
|
if (kstrtou32(acpi_device_uid(hb), 0, &uid))
|
|
return -EINVAL;
|
|
|
|
return acpi_get_genport_coordinates(uid, dport->coord);
|
|
}
|
|
|
|
static int add_host_bridge_dport(struct device *match, void *arg)
|
|
{
|
|
int ret;
|
|
acpi_status rc;
|
|
struct device *bridge;
|
|
struct cxl_dport *dport;
|
|
struct cxl_chbs_context ctx;
|
|
struct acpi_pci_root *pci_root;
|
|
struct cxl_port *root_port = arg;
|
|
struct device *host = root_port->dev.parent;
|
|
struct acpi_device *hb = to_cxl_host_bridge(host, match);
|
|
|
|
if (!hb)
|
|
return 0;
|
|
|
|
rc = cxl_get_chbs(match, hb, &ctx);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (ctx.cxl_version == UINT_MAX) {
|
|
dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",
|
|
ctx.uid);
|
|
return 0;
|
|
}
|
|
|
|
if (ctx.base == CXL_RESOURCE_NONE) {
|
|
dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n",
|
|
ctx.uid);
|
|
return 0;
|
|
}
|
|
|
|
pci_root = acpi_pci_find_root(hb->handle);
|
|
bridge = pci_root->bus->bridge;
|
|
|
|
/*
|
|
* In RCH mode, bind the component regs base to the dport. In
|
|
* VH mode it will be bound to the CXL host bridge's port
|
|
* object later in add_host_bridge_uport().
|
|
*/
|
|
if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
|
|
dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid,
|
|
&ctx.base);
|
|
dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,
|
|
ctx.base);
|
|
} else {
|
|
dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,
|
|
CXL_RESOURCE_NONE);
|
|
}
|
|
|
|
if (IS_ERR(dport))
|
|
return PTR_ERR(dport);
|
|
|
|
ret = get_genport_coordinates(match, dport);
|
|
if (ret)
|
|
dev_dbg(match, "Failed to get generic port perf coordinates.\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* A host bridge is a dport to a CFMWS decode and it is a uport to the
|
|
* dport (PCIe Root Ports) in the host bridge.
|
|
*/
|
|
static int add_host_bridge_uport(struct device *match, void *arg)
|
|
{
|
|
struct cxl_port *root_port = arg;
|
|
struct device *host = root_port->dev.parent;
|
|
struct acpi_device *hb = to_cxl_host_bridge(host, match);
|
|
struct acpi_pci_root *pci_root;
|
|
struct cxl_dport *dport;
|
|
struct cxl_port *port;
|
|
struct device *bridge;
|
|
struct cxl_chbs_context ctx;
|
|
resource_size_t component_reg_phys;
|
|
int rc;
|
|
|
|
if (!hb)
|
|
return 0;
|
|
|
|
pci_root = acpi_pci_find_root(hb->handle);
|
|
bridge = pci_root->bus->bridge;
|
|
dport = cxl_find_dport_by_dev(root_port, bridge);
|
|
if (!dport) {
|
|
dev_dbg(host, "host bridge expected and not found\n");
|
|
return 0;
|
|
}
|
|
|
|
if (dport->rch) {
|
|
dev_info(bridge, "host supports CXL (restricted)\n");
|
|
return 0;
|
|
}
|
|
|
|
rc = cxl_get_chbs(match, hb, &ctx);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
|
|
dev_warn(bridge,
|
|
"CXL CHBS version mismatch, skip port registration\n");
|
|
return 0;
|
|
}
|
|
|
|
component_reg_phys = ctx.base;
|
|
if (component_reg_phys != CXL_RESOURCE_NONE)
|
|
dev_dbg(match, "CHBCR found for UID %lld: %pa\n",
|
|
ctx.uid, &component_reg_phys);
|
|
|
|
rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
|
|
if (rc)
|
|
return rc;
|
|
|
|
port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
|
|
if (IS_ERR(port))
|
|
return PTR_ERR(port);
|
|
|
|
dev_info(bridge, "host supports CXL\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int add_root_nvdimm_bridge(struct device *match, void *data)
|
|
{
|
|
struct cxl_decoder *cxld;
|
|
struct cxl_port *root_port = data;
|
|
struct cxl_nvdimm_bridge *cxl_nvb;
|
|
struct device *host = root_port->dev.parent;
|
|
|
|
if (!is_root_decoder(match))
|
|
return 0;
|
|
|
|
cxld = to_cxl_decoder(match);
|
|
if (!(cxld->flags & CXL_DECODER_F_PMEM))
|
|
return 0;
|
|
|
|
cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
|
|
if (IS_ERR(cxl_nvb)) {
|
|
dev_dbg(host, "failed to register pmem\n");
|
|
return PTR_ERR(cxl_nvb);
|
|
}
|
|
dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
|
|
dev_name(&cxl_nvb->dev));
|
|
return 1;
|
|
}
|
|
|
|
static struct lock_class_key cxl_root_key;
|
|
|
|
static void cxl_acpi_lock_reset_class(void *dev)
|
|
{
|
|
device_lock_reset_class(dev);
|
|
}
|
|
|
|
static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
|
|
{
|
|
priv->desc = (unsigned long) pub;
|
|
}
|
|
|
|
static struct resource *cxl_get_public_resource(struct resource *priv)
|
|
{
|
|
return (struct resource *) priv->desc;
|
|
}
|
|
|
|
static void remove_cxl_resources(void *data)
|
|
{
|
|
struct resource *res, *next, *cxl = data;
|
|
|
|
for (res = cxl->child; res; res = next) {
|
|
struct resource *victim = cxl_get_public_resource(res);
|
|
|
|
next = res->sibling;
|
|
remove_resource(res);
|
|
|
|
if (victim) {
|
|
remove_resource(victim);
|
|
kfree(victim);
|
|
}
|
|
|
|
del_cxl_resource(res);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
|
|
* @cxl_res: A standalone resource tree where each CXL window is a sibling
|
|
*
|
|
* Walk each CXL window in @cxl_res and add it to iomem_resource potentially
|
|
* expanding its boundaries to ensure that any conflicting resources become
|
|
* children. If a window is expanded it may then conflict with a another window
|
|
* entry and require the window to be truncated or trimmed. Consider this
|
|
* situation:
|
|
*
|
|
* |-- "CXL Window 0" --||----- "CXL Window 1" -----|
|
|
* |--------------- "System RAM" -------------|
|
|
*
|
|
* ...where platform firmware has established as System RAM resource across 2
|
|
* windows, but has left some portion of window 1 for dynamic CXL region
|
|
* provisioning. In this case "Window 0" will span the entirety of the "System
|
|
* RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
|
|
* of that "System RAM" resource.
|
|
*/
|
|
static int add_cxl_resources(struct resource *cxl_res)
|
|
{
|
|
struct resource *res, *new, *next;
|
|
|
|
for (res = cxl_res->child; res; res = next) {
|
|
new = kzalloc(sizeof(*new), GFP_KERNEL);
|
|
if (!new)
|
|
return -ENOMEM;
|
|
new->name = res->name;
|
|
new->start = res->start;
|
|
new->end = res->end;
|
|
new->flags = IORESOURCE_MEM;
|
|
new->desc = IORES_DESC_CXL;
|
|
|
|
/*
|
|
* Record the public resource in the private cxl_res tree for
|
|
* later removal.
|
|
*/
|
|
cxl_set_public_resource(res, new);
|
|
|
|
insert_resource_expand_to_fit(&iomem_resource, new);
|
|
|
|
next = res->sibling;
|
|
while (next && resource_overlaps(new, next)) {
|
|
if (resource_contains(new, next)) {
|
|
struct resource *_next = next->sibling;
|
|
|
|
remove_resource(next);
|
|
del_cxl_resource(next);
|
|
next = _next;
|
|
} else
|
|
next->start = new->end + 1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int pair_cxl_resource(struct device *dev, void *data)
|
|
{
|
|
struct resource *cxl_res = data;
|
|
struct resource *p;
|
|
|
|
if (!is_root_decoder(dev))
|
|
return 0;
|
|
|
|
for (p = cxl_res->child; p; p = p->sibling) {
|
|
struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
|
|
struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
|
|
struct resource res = {
|
|
.start = cxld->hpa_range.start,
|
|
.end = cxld->hpa_range.end,
|
|
.flags = IORESOURCE_MEM,
|
|
};
|
|
|
|
if (resource_contains(p, &res)) {
|
|
cxlrd->res = cxl_get_public_resource(p);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cxl_acpi_probe(struct platform_device *pdev)
|
|
{
|
|
int rc;
|
|
struct resource *cxl_res;
|
|
struct cxl_root *cxl_root;
|
|
struct cxl_port *root_port;
|
|
struct device *host = &pdev->dev;
|
|
struct acpi_device *adev = ACPI_COMPANION(host);
|
|
struct cxl_cfmws_context ctx;
|
|
|
|
device_lock_set_class(&pdev->dev, &cxl_root_key);
|
|
rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
|
|
&pdev->dev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
|
|
if (!cxl_res)
|
|
return -ENOMEM;
|
|
cxl_res->name = "CXL mem";
|
|
cxl_res->start = 0;
|
|
cxl_res->end = -1;
|
|
cxl_res->flags = IORESOURCE_MEM;
|
|
|
|
cxl_root = devm_cxl_add_root(host, &acpi_root_ops);
|
|
if (IS_ERR(cxl_root))
|
|
return PTR_ERR(cxl_root);
|
|
root_port = &cxl_root->port;
|
|
|
|
rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
|
|
add_host_bridge_dport);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
|
|
if (rc)
|
|
return rc;
|
|
|
|
ctx = (struct cxl_cfmws_context) {
|
|
.dev = host,
|
|
.root_port = root_port,
|
|
.cxl_res = cxl_res,
|
|
};
|
|
rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
|
|
if (rc < 0)
|
|
return -ENXIO;
|
|
|
|
rc = add_cxl_resources(cxl_res);
|
|
if (rc)
|
|
return rc;
|
|
|
|
/*
|
|
* Populate the root decoders with their related iomem resource,
|
|
* if present
|
|
*/
|
|
device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
|
|
|
|
/*
|
|
* Root level scanned with host-bridge as dports, now scan host-bridges
|
|
* for their role as CXL uports to their CXL-capable PCIe Root Ports.
|
|
*/
|
|
rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
|
|
add_host_bridge_uport);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
if (IS_ENABLED(CONFIG_CXL_PMEM))
|
|
rc = device_for_each_child(&root_port->dev, root_port,
|
|
add_root_nvdimm_bridge);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
/* In case PCI is scanned before ACPI re-trigger memdev attach */
|
|
cxl_bus_rescan();
|
|
return 0;
|
|
}
|
|
|
|
static const struct acpi_device_id cxl_acpi_ids[] = {
|
|
{ "ACPI0017" },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
|
|
|
|
static const struct platform_device_id cxl_test_ids[] = {
|
|
{ "cxl_acpi" },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, cxl_test_ids);
|
|
|
|
static struct platform_driver cxl_acpi_driver = {
|
|
.probe = cxl_acpi_probe,
|
|
.driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.acpi_match_table = cxl_acpi_ids,
|
|
},
|
|
.id_table = cxl_test_ids,
|
|
};
|
|
|
|
static int __init cxl_acpi_init(void)
|
|
{
|
|
return platform_driver_register(&cxl_acpi_driver);
|
|
}
|
|
|
|
static void __exit cxl_acpi_exit(void)
|
|
{
|
|
platform_driver_unregister(&cxl_acpi_driver);
|
|
cxl_bus_drain();
|
|
}
|
|
|
|
/* load before dax_hmem sees 'Soft Reserved' CXL ranges */
|
|
subsys_initcall(cxl_acpi_init);
|
|
module_exit(cxl_acpi_exit);
|
|
MODULE_DESCRIPTION("CXL ACPI: Platform Support");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_IMPORT_NS(CXL);
|
|
MODULE_IMPORT_NS(ACPI);
|