14cba6ace7
amd_rng_mod_init() uses pci_read_config_dword() that returns PCIBIOS_*
codes. The return code is then returned as is but amd_rng_mod_init() is
a module_init() function that should return normal errnos.
Convert PCIBIOS_* returns code using pcibios_err_to_errno() into normal
errno before returning it.
Fixes: 96d63c0297
("[PATCH] Add AMD HW RNG driver")
Cc: stable@vger.kernel.org
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
223 lines
4.8 KiB
C
223 lines
4.8 KiB
C
/*
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* RNG driver for AMD RNGs
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*
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* Copyright 2005 (c) MontaVista Software, Inc.
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*
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* with the majority of the code coming from:
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*
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* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
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* (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
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*
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* derived from
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*
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* Hardware driver for the AMD 768 Random Number Generator (RNG)
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* (c) Copyright 2001 Red Hat Inc
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*
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* derived from
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*
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* Hardware driver for Intel i810 Random Number Generator (RNG)
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* Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
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* Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/delay.h>
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#include <linux/hw_random.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#define DRV_NAME "AMD768-HWRNG"
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#define RNGDATA 0x00
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#define RNGDONE 0x04
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#define PMBASE_OFFSET 0xF0
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#define PMBASE_SIZE 8
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/*
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* Data for PCI driver interface
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*
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* This data only exists for exporting the supported
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* PCI ids via MODULE_DEVICE_TABLE. We do not actually
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* register a pci_driver, because someone else might one day
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* want to register another driver on the same PCI id.
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*/
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static const struct pci_device_id pci_tbl[] = {
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{ PCI_VDEVICE(AMD, 0x7443), 0, },
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{ PCI_VDEVICE(AMD, 0x746b), 0, },
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{ 0, }, /* terminate list */
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};
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MODULE_DEVICE_TABLE(pci, pci_tbl);
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struct amd768_priv {
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void __iomem *iobase;
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struct pci_dev *pcidev;
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u32 pmbase;
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};
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static int amd_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
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{
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u32 *data = buf;
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struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
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size_t read = 0;
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/* We will wait at maximum one time per read */
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int timeout = max / 4 + 1;
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/*
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* RNG data is available when RNGDONE is set to 1
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* New random numbers are generated approximately 128 microseconds
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* after RNGDATA is read
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*/
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while (read < max) {
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if (ioread32(priv->iobase + RNGDONE) == 0) {
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if (wait) {
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/* Delay given by datasheet */
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usleep_range(128, 196);
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if (timeout-- == 0)
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return read;
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} else {
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return 0;
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}
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} else {
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*data = ioread32(priv->iobase + RNGDATA);
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data++;
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read += 4;
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}
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}
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return read;
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}
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static int amd_rng_init(struct hwrng *rng)
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{
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struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
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u8 rnen;
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pci_read_config_byte(priv->pcidev, 0x40, &rnen);
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rnen |= BIT(7); /* RNG on */
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pci_write_config_byte(priv->pcidev, 0x40, rnen);
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pci_read_config_byte(priv->pcidev, 0x41, &rnen);
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rnen |= BIT(7); /* PMIO enable */
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pci_write_config_byte(priv->pcidev, 0x41, rnen);
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return 0;
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}
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static void amd_rng_cleanup(struct hwrng *rng)
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{
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struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
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u8 rnen;
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pci_read_config_byte(priv->pcidev, 0x40, &rnen);
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rnen &= ~BIT(7); /* RNG off */
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pci_write_config_byte(priv->pcidev, 0x40, rnen);
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}
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static struct hwrng amd_rng = {
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.name = "amd",
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.init = amd_rng_init,
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.cleanup = amd_rng_cleanup,
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.read = amd_rng_read,
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};
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static int __init amd_rng_mod_init(void)
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{
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int err;
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struct pci_dev *pdev = NULL;
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const struct pci_device_id *ent;
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u32 pmbase;
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struct amd768_priv *priv;
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for_each_pci_dev(pdev) {
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ent = pci_match_id(pci_tbl, pdev);
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if (ent)
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goto found;
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}
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/* Device not found. */
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return -ENODEV;
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found:
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err = pci_read_config_dword(pdev, 0x58, &pmbase);
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if (err) {
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err = pcibios_err_to_errno(err);
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goto put_dev;
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}
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pmbase &= 0x0000FF00;
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if (pmbase == 0) {
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err = -EIO;
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goto put_dev;
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}
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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err = -ENOMEM;
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goto put_dev;
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}
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if (!request_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE, DRV_NAME)) {
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dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
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pmbase + 0xF0);
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err = -EBUSY;
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goto out;
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}
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priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
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if (!priv->iobase) {
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pr_err(DRV_NAME "Cannot map ioport\n");
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err = -EINVAL;
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goto err_iomap;
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}
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amd_rng.priv = (unsigned long)priv;
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priv->pmbase = pmbase;
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priv->pcidev = pdev;
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pr_info(DRV_NAME " detected\n");
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err = hwrng_register(&amd_rng);
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if (err) {
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pr_err(DRV_NAME " registering failed (%d)\n", err);
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goto err_hwrng;
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}
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return 0;
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err_hwrng:
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ioport_unmap(priv->iobase);
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err_iomap:
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release_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
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out:
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kfree(priv);
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put_dev:
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pci_dev_put(pdev);
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return err;
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}
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static void __exit amd_rng_mod_exit(void)
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{
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struct amd768_priv *priv;
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priv = (struct amd768_priv *)amd_rng.priv;
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hwrng_unregister(&amd_rng);
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ioport_unmap(priv->iobase);
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release_region(priv->pmbase + PMBASE_OFFSET, PMBASE_SIZE);
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pci_dev_put(priv->pcidev);
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kfree(priv);
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}
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module_init(amd_rng_mod_init);
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module_exit(amd_rng_mod_exit);
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MODULE_AUTHOR("The Linux Kernel team");
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MODULE_DESCRIPTION("H/W RNG driver for AMD chipsets");
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MODULE_LICENSE("GPL");
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