b20d9a73a3
The nx driver started out its life as a BE-only driver. However, somewhere along the way LE support was partially added. This never seems to have been extended all the way but it does trigger numerous warnings during build. This patch fixes all those warnings, but it doesn't mean that the driver will work on LE. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
207 lines
4.1 KiB
C
207 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __NX_CSBCPB_H__
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#define __NX_CSBCPB_H__
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struct cop_symcpb_aes_ecb {
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u8 key[32];
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u8 __rsvd[80];
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} __packed;
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struct cop_symcpb_aes_cbc {
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u8 iv[16];
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u8 key[32];
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u8 cv[16];
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u32 spbc;
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u8 __rsvd[44];
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} __packed;
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struct cop_symcpb_aes_gca {
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u8 in_pat[16];
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u8 key[32];
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u8 out_pat[16];
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u32 spbc;
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u8 __rsvd[44];
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} __packed;
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struct cop_symcpb_aes_gcm {
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u8 in_pat_or_aad[16];
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u8 iv_or_cnt[16];
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u64 bit_length_aad;
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u64 bit_length_data;
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u8 in_s0[16];
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u8 key[32];
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u8 __rsvd1[16];
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u8 out_pat_or_mac[16];
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u8 out_s0[16];
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u8 out_cnt[16];
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u32 spbc;
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u8 __rsvd2[12];
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} __packed;
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struct cop_symcpb_aes_ctr {
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u8 iv[16];
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u8 key[32];
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u8 cv[16];
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u32 spbc;
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u8 __rsvd2[44];
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} __packed;
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struct cop_symcpb_aes_cca {
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u8 b0[16];
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u8 b1[16];
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u8 key[16];
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u8 out_pat_or_b0[16];
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u32 spbc;
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u8 __rsvd[44];
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} __packed;
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struct cop_symcpb_aes_ccm {
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u8 in_pat_or_b0[16];
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u8 iv_or_ctr[16];
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u8 in_s0[16];
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u8 key[16];
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u8 __rsvd1[48];
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u8 out_pat_or_mac[16];
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u8 out_s0[16];
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u8 out_ctr[16];
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u32 spbc;
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u8 __rsvd2[12];
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} __packed;
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struct cop_symcpb_aes_xcbc {
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u8 cv[16];
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u8 key[16];
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u8 __rsvd1[16];
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u8 out_cv_mac[16];
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u32 spbc;
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u8 __rsvd2[44];
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} __packed;
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struct cop_symcpb_sha256 {
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u64 message_bit_length;
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u64 __rsvd1;
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u8 input_partial_digest[32];
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u8 message_digest[32];
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u32 spbc;
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u8 __rsvd2[44];
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} __packed;
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struct cop_symcpb_sha512 {
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u64 message_bit_length_hi;
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u64 message_bit_length_lo;
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u8 input_partial_digest[64];
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u8 __rsvd1[32];
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u8 message_digest[64];
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u32 spbc;
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u8 __rsvd2[76];
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} __packed;
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#define NX_FDM_INTERMEDIATE 0x01
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#define NX_FDM_CONTINUATION 0x02
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#define NX_FDM_ENDE_ENCRYPT 0x80
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#define NX_CPB_FDM(c) ((c)->cpb.hdr.fdm)
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#define NX_CPB_KS_DS(c) ((c)->cpb.hdr.ks_ds)
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#define NX_CPB_KEY_SIZE(c) (NX_CPB_KS_DS(c) >> 4)
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#define NX_CPB_SET_KEY_SIZE(c, x) NX_CPB_KS_DS(c) |= ((x) << 4)
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#define NX_CPB_SET_DIGEST_SIZE(c, x) NX_CPB_KS_DS(c) |= (x)
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struct cop_symcpb_header {
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u8 mode;
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u8 fdm;
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u8 ks_ds;
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u8 pad_byte;
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u8 __rsvd[12];
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} __packed;
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struct cop_parameter_block {
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struct cop_symcpb_header hdr;
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union {
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struct cop_symcpb_aes_ecb aes_ecb;
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struct cop_symcpb_aes_cbc aes_cbc;
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struct cop_symcpb_aes_gca aes_gca;
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struct cop_symcpb_aes_gcm aes_gcm;
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struct cop_symcpb_aes_cca aes_cca;
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struct cop_symcpb_aes_ccm aes_ccm;
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struct cop_symcpb_aes_ctr aes_ctr;
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struct cop_symcpb_aes_xcbc aes_xcbc;
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struct cop_symcpb_sha256 sha256;
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struct cop_symcpb_sha512 sha512;
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};
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} __packed;
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#define NX_CSB_VALID_BIT 0x80
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/* co-processor status block */
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struct cop_status_block {
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u8 valid;
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u8 crb_seq_number;
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u8 completion_code;
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u8 completion_extension;
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__be32 processed_byte_count;
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__be64 address;
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} __packed;
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/* Nest accelerator workbook section 4.4 */
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struct nx_csbcpb {
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unsigned char __rsvd[112];
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struct cop_status_block csb;
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struct cop_parameter_block cpb;
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} __packed;
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/* nx_csbcpb related definitions */
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#define NX_MODE_AES_ECB 0
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#define NX_MODE_AES_CBC 1
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#define NX_MODE_AES_GMAC 2
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#define NX_MODE_AES_GCA 3
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#define NX_MODE_AES_GCM 4
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#define NX_MODE_AES_CCA 5
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#define NX_MODE_AES_CCM 6
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#define NX_MODE_AES_CTR 7
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#define NX_MODE_AES_XCBC_MAC 20
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#define NX_MODE_SHA 0
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#define NX_MODE_SHA_HMAC 1
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#define NX_MODE_AES_CBC_HMAC_ETA 8
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#define NX_MODE_AES_CBC_HMAC_ATE 9
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#define NX_MODE_AES_CBC_HMAC_EAA 10
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#define NX_MODE_AES_CTR_HMAC_ETA 12
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#define NX_MODE_AES_CTR_HMAC_ATE 13
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#define NX_MODE_AES_CTR_HMAC_EAA 14
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#define NX_FDM_CI_FULL 0
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#define NX_FDM_CI_FIRST 1
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#define NX_FDM_CI_LAST 2
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#define NX_FDM_CI_MIDDLE 3
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#define NX_FDM_PR_NONE 0
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#define NX_FDM_PR_PAD 1
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#define NX_KS_AES_128 1
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#define NX_KS_AES_192 2
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#define NX_KS_AES_256 3
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#define NX_DS_SHA256 2
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#define NX_DS_SHA512 3
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#define NX_FC_AES 0
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#define NX_FC_SHA 2
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#define NX_FC_AES_HMAC 6
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#define NX_MAX_FC (NX_FC_AES_HMAC + 1)
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#define NX_MAX_MODE (NX_MODE_AES_XCBC_MAC + 1)
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#define HCOP_FC_AES NX_FC_AES
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#define HCOP_FC_SHA NX_FC_SHA
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#define HCOP_FC_AES_HMAC NX_FC_AES_HMAC
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/* indices into the array of algorithm properties */
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#define NX_PROPS_AES_128 0
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#define NX_PROPS_AES_192 1
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#define NX_PROPS_AES_256 2
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#define NX_PROPS_SHA256 1
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#define NX_PROPS_SHA512 2
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#endif
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