9924003807
As far as I can tell, "crc32c-sparc64" is the only "shash" algorithm in the kernel that sets a nonzero alignmask and actually relies on it to get the crypto API to align the inputs and outputs. This capability is not really useful, though. To unblock removing the support for alignmask from shash_alg, this patch updates crc32c-sparc64 to no longer use the alignmask. This means doing 8-byte alignment of the data when doing an update, using get_unaligned_le32() when setting a non-default initial CRC, and using put_unaligned_le32() to output the final CRC. Partially tested with: export ARCH=sparc64 CROSS_COMPILE=sparc64-linux-gnu- make sparc64_defconfig echo CONFIG_CRYPTO_CRC32C_SPARC64=y >> .config echo '# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set' >> .config echo CONFIG_DEBUG_KERNEL=y >> .config echo CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y >> .config make olddefconfig make -j$(getconf _NPROCESSORS_ONLN) qemu-system-sparc64 -kernel arch/sparc/boot/image -nographic However, qemu doesn't actually support the sparc CRC32C instructions, so for the test I temporarily replaced crc32c_sparc64() with __crc32c_le() and made sparc64_has_crc32c_opcode() always return true. So essentially I tested the glue code, not the actual SPARC part which is unchanged. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
185 lines
4.1 KiB
C
185 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Glue code for CRC32C optimized for sparc64 crypto opcodes.
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*
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* This is based largely upon arch/x86/crypto/crc32c-intel.c
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*
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* Copyright (C) 2008 Intel Corporation
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* Authors: Austin Zhang <austin_zhang@linux.intel.com>
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* Kent Liu <kent.liu@intel.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/crc32.h>
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#include <crypto/internal/hash.h>
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#include <asm/pstate.h>
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#include <asm/elf.h>
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#include <asm/unaligned.h>
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#include "opcodes.h"
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/*
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* Setting the seed allows arbitrary accumulators and flexible XOR policy
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* If your algorithm starts with ~0, then XOR with ~0 before you set
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* the seed.
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*/
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static int crc32c_sparc64_setkey(struct crypto_shash *hash, const u8 *key,
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unsigned int keylen)
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{
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u32 *mctx = crypto_shash_ctx(hash);
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if (keylen != sizeof(u32))
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return -EINVAL;
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*mctx = get_unaligned_le32(key);
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return 0;
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}
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static int crc32c_sparc64_init(struct shash_desc *desc)
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{
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u32 *mctx = crypto_shash_ctx(desc->tfm);
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u32 *crcp = shash_desc_ctx(desc);
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*crcp = *mctx;
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return 0;
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}
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extern void crc32c_sparc64(u32 *crcp, const u64 *data, unsigned int len);
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static u32 crc32c_compute(u32 crc, const u8 *data, unsigned int len)
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{
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unsigned int n = -(uintptr_t)data & 7;
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if (n) {
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/* Data isn't 8-byte aligned. Align it. */
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n = min(n, len);
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crc = __crc32c_le(crc, data, n);
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data += n;
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len -= n;
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}
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n = len & ~7U;
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if (n) {
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crc32c_sparc64(&crc, (const u64 *)data, n);
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data += n;
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len -= n;
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}
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if (len)
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crc = __crc32c_le(crc, data, len);
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return crc;
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}
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static int crc32c_sparc64_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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u32 *crcp = shash_desc_ctx(desc);
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*crcp = crc32c_compute(*crcp, data, len);
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return 0;
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}
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static int __crc32c_sparc64_finup(const u32 *crcp, const u8 *data,
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unsigned int len, u8 *out)
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{
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put_unaligned_le32(~crc32c_compute(*crcp, data, len), out);
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return 0;
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}
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static int crc32c_sparc64_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return __crc32c_sparc64_finup(shash_desc_ctx(desc), data, len, out);
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}
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static int crc32c_sparc64_final(struct shash_desc *desc, u8 *out)
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{
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u32 *crcp = shash_desc_ctx(desc);
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put_unaligned_le32(~*crcp, out);
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return 0;
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}
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static int crc32c_sparc64_digest(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return __crc32c_sparc64_finup(crypto_shash_ctx(desc->tfm), data, len,
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out);
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}
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static int crc32c_sparc64_cra_init(struct crypto_tfm *tfm)
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{
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u32 *key = crypto_tfm_ctx(tfm);
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*key = ~0;
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return 0;
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}
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#define CHKSUM_BLOCK_SIZE 1
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#define CHKSUM_DIGEST_SIZE 4
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static struct shash_alg alg = {
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.setkey = crc32c_sparc64_setkey,
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.init = crc32c_sparc64_init,
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.update = crc32c_sparc64_update,
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.final = crc32c_sparc64_final,
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.finup = crc32c_sparc64_finup,
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.digest = crc32c_sparc64_digest,
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.descsize = sizeof(u32),
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.digestsize = CHKSUM_DIGEST_SIZE,
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.base = {
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.cra_name = "crc32c",
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.cra_driver_name = "crc32c-sparc64",
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.cra_priority = SPARC_CR_OPCODE_PRIORITY,
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.cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
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.cra_blocksize = CHKSUM_BLOCK_SIZE,
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.cra_ctxsize = sizeof(u32),
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.cra_module = THIS_MODULE,
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.cra_init = crc32c_sparc64_cra_init,
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}
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};
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static bool __init sparc64_has_crc32c_opcode(void)
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{
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unsigned long cfr;
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if (!(sparc64_elf_hwcap & HWCAP_SPARC_CRYPTO))
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return false;
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__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
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if (!(cfr & CFR_CRC32C))
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return false;
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return true;
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}
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static int __init crc32c_sparc64_mod_init(void)
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{
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if (sparc64_has_crc32c_opcode()) {
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pr_info("Using sparc64 crc32c opcode optimized CRC32C implementation\n");
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return crypto_register_shash(&alg);
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}
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pr_info("sparc64 crc32c opcode not available.\n");
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return -ENODEV;
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}
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static void __exit crc32c_sparc64_mod_fini(void)
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{
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crypto_unregister_shash(&alg);
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}
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module_init(crc32c_sparc64_mod_init);
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module_exit(crc32c_sparc64_mod_fini);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("CRC32c (Castagnoli), sparc64 crc32c opcode accelerated");
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MODULE_ALIAS_CRYPTO("crc32c");
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#include "crop_devid.c"
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