d0ba3922ae
Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
186 lines
5.1 KiB
ArmAsm
186 lines
5.1 KiB
ArmAsm
/*
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* linux/arch/arm/mach-omap3/sram.S
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*
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* Omap3 specific functions that need to be run in internal SRAM
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*
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* (C) Copyright 2007
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* Texas Instruments Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include "sdrc.h"
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#include "cm.h"
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.text
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/*
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* Change frequency of core dpll
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* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
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* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
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* SDRC rates < 83MHz
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* r5 = number of MPU cycles to wait for SDRC to stabilize after
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* reprogramming the SDRC when switching to a slower MPU speed
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* r6 = SDRC_MR_0 register value
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*
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*/
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ENTRY(omap3_sram_configure_core_dpll)
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stmfd sp!, {r1-r12, lr} @ store regs to stack
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ldr r4, [sp, #52] @ pull extra args off the stack
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ldr r5, [sp, #56] @ load extra args from the stack
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ldr r6, [sp, #60] @ load extra args from the stack
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dsb @ flush buffered writes to interconnect
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cmp r3, #0x2
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blne configure_sdrc
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cmp r4, #0x1
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bleq unlock_dll
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blne lock_dll
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bl sdram_in_selfrefresh @ put the SDRAM in self refresh
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bl configure_core_dpll
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bl enable_sdrc
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cmp r4, #0x1
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bleq wait_dll_unlock
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blne wait_dll_lock
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cmp r3, #0x1
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beq return_to_sdram
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bl configure_sdrc
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mov r12, r5 @ if slowing, wait for SDRC to stabilize
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bl wait_clk_stable
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return_to_sdram:
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isb @ prevent speculative exec past here
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mov r0, #0 @ return value
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ldmfd sp!, {r1-r12, pc} @ restore regs and return
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unlock_dll:
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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orr r12, r12, #0x4
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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lock_dll:
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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bic r12, r12, #0x4
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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sdram_in_selfrefresh:
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ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
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ldr r12, [r11] @ read the contents of SDRC_POWER
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mov r9, r12 @ keep a copy of SDRC_POWER bits
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orr r12, r12, #0x40 @ enable self refresh on idle req
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bic r12, r12, #0x4 @ clear PWDENA
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str r12, [r11] @ write back to SDRC_POWER register
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ldr r12, [r11] @ posted-write barrier for SDRC
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ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
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ldr r12, [r11]
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bic r12, r12, #0x2 @ disable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle:
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #0x2 @ check for SDRC idle
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cmp r12, #2
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bne wait_sdrc_idle
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bx lr
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configure_core_dpll:
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ldr r11, omap3_cm_clksel1_pll
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ldr r12, [r11]
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ldr r10, core_m2_mask_val @ modify m2 for core dpll
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and r12, r12, r10
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orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
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str r12, [r11]
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ldr r12, [r11] @ posted-write barrier for CM
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bx lr
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wait_clk_stable:
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subs r12, r12, #1
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bne wait_clk_stable
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bx lr
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enable_sdrc:
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ldr r11, omap3_cm_iclken1_core
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ldr r12, [r11]
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orr r12, r12, #0x2 @ enable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle1:
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #0x2
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cmp r12, #0
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bne wait_sdrc_idle1
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restore_sdrc_power_val:
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ldr r11, omap3_sdrc_power
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str r9, [r11] @ restore SDRC_POWER, no barrier needed
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bx lr
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wait_dll_lock:
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #0x4
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cmp r12, #0x4
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bne wait_dll_lock
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bx lr
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wait_dll_unlock:
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #0x4
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cmp r12, #0x0
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bne wait_dll_unlock
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bx lr
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configure_sdrc:
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ldr r11, omap3_sdrc_rfr_ctrl
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str r0, [r11]
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ldr r11, omap3_sdrc_actim_ctrla
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str r1, [r11]
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ldr r11, omap3_sdrc_actim_ctrlb
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str r2, [r11]
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ldr r11, omap3_sdrc_mr_0
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str r6, [r11]
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ldr r6, [r11] @ posted-write barrier for SDRC
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bx lr
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omap3_sdrc_power:
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.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
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omap3_cm_clksel1_pll:
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.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
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omap3_cm_idlest1_core:
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.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
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omap3_cm_iclken1_core:
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.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
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omap3_sdrc_rfr_ctrl:
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.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
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omap3_sdrc_actim_ctrla:
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.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
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omap3_sdrc_actim_ctrlb:
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.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
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omap3_sdrc_mr_0:
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.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
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omap3_sdrc_dlla_status:
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.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
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omap3_sdrc_dlla_ctrl:
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.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
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core_m2_mask_val:
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.word 0x07FFFFFF
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ENTRY(omap3_sram_configure_core_dpll_sz)
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.word . - omap3_sram_configure_core_dpll
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