1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
649 lines
29 KiB
C
649 lines
29 KiB
C
/*******************************************************************************
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*
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* (c) 1999 by Computone Corporation
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*
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********************************************************************************
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*
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*
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* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
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* serial I/O controllers.
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*
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* DESCRIPTION: Definitions limited to properties of the hardware or the
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* bootstrap firmware. As such, they are applicable regardless of
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* operating system or loadware (standard or diagnostic).
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*
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*******************************************************************************/
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#ifndef I2HW_H
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#define I2HW_H 1
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//------------------------------------------------------------------------------
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// Revision History:
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//
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// 23 September 1991 MAG First Draft Started...through...
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// 11 October 1991 ... Continuing development...
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// 6 August 1993 Added support for ISA-4 (asic) which is architected
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// as an ISA-CEX with a single 4-port box.
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//
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// 20 December 1996 AKM Version for Linux
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//
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//------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------
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HARDWARE DESCRIPTION:
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Introduction:
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The IntelliPort-II and IntelliPort-IIEX products occupy a block of eight (8)
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addresses in the host's I/O space.
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Some addresses are used to transfer data to/from the board, some to transfer
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so-called "mailbox" messages, and some to read bit-mapped status information.
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While all the products in the line are functionally similar, some use a 16-bit
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data path to transfer data while others use an 8-bit path. Also, the use of
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command /status/mailbox registers differs slightly between the II and IIEX
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branches of the family.
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The host determines what type of board it is dealing with by reading a string of
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sixteen characters from the board. These characters are always placed in the
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fifo by the board's local processor whenever the board is reset (either from
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power-on or under software control) and are known as the "Power-on Reset
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Message." In order that this message can be read from either type of board, the
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hardware registers used in reading this message are the same. Once this message
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has been read by the host, then it has the information required to operate.
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General Differences between boards:
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The greatest structural difference is between the -II and -IIEX families of
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product. The -II boards use the Am4701 dual 512x8 bidirectional fifo to support
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the data path, mailbox registers, and status registers. This chip contains some
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features which are not used in the IntelliPort-II products; a description of
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these is omitted here. Because of these many features, it contains many
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registers, too many to access directly within a small address space. They are
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accessed by first writing a value to a "pointer" register. This value selects
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the register to be accessed. The next read or write to that address accesses
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the selected register rather than the pointer register.
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The -IIEX boards use a proprietary design similar to the Am4701 in function. But
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because of a simpler, more streamlined design it doesn't require so many
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registers. This means they can be accessed directly in single operations rather
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than through a pointer register.
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Besides these differences, there are differences in whether 8-bit or 16-bit
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transfers are used to move data to the board.
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The -II boards are capable only of 8-bit data transfers, while the -IIEX boards
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may be configured for either 8-bit or 16-bit data transfers. If the on-board DIP
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switch #8 is ON, and the card has been installed in a 16-bit slot, 16-bit
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transfers are supported (and will be expected by the standard loadware). The
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on-board firmware can determine the position of the switch, and whether the
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board is installed in a 16-bit slot; it supplies this information to the host as
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part of the power-up reset message.
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The configuration switch (#8) and slot selection do not directly configure the
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hardware. It is up to the on-board loadware and host-based drivers to act
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according to the selected options. That is, loadware and drivers could be
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written to perform 8-bit transfers regardless of the state of the DIP switch or
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slot (and in a diagnostic environment might well do so). Likewise, 16-bit
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transfers could be performed as long as the card is in a 16-bit slot.
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Note the slot selection and DIP switch selection are provided separately: a
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board running in 8-bit mode in a 16-bit slot has a greater range of possible
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interrupts to choose from; information of potential use to the host.
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All 8-bit data transfers are done in the same way, regardless of whether on a
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-II board or a -IIEX board.
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The host must consider two things then: 1) whether a -II or -IIEX product is
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being used, and 2) whether an 8-bit or 16-bit data path is used.
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A further difference is that -II boards always have a 512-byte fifo operating in
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each direction. -IIEX boards may use fifos of varying size; this size is
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reported as part of the power-up message.
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I/O Map Of IntelliPort-II and IntelliPort-IIEX boards:
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(Relative to the chosen base address)
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Addr R/W IntelliPort-II IntelliPort-IIEX
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---- --- -------------- ----------------
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0 R/W Data Port (byte) Data Port (byte or word)
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1 R/W (Not used) (MSB of word-wide data written to Data Port)
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2 R Status Register Status Register
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2 W Pointer Register Interrupt Mask Register
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3 R/W (Not used) Mailbox Registers (6 bits: 11111100)
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4,5 -- Reserved for future products
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6 -- Reserved for future products
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7 R Guaranteed to have no effect
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7 W Hardware reset of board.
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Rules:
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All data transfers are performed using the even i/o address. If byte-wide data
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transfers are being used, do INB/OUTB operations on the data port. If word-wide
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transfers are used, do INW/OUTW operations. In some circumstances (such as
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reading the power-up message) you will do INB from the data port, but in this
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case the MSB of each word read is lost. When accessing all other unreserved
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registers, use byte operations only.
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------------------------------------------------------------------------------*/
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//------------------------------------------------
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// Mandatory Includes:
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//------------------------------------------------
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//
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#include "ip2types.h"
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#include "i2os.h" /* For any o.s., compiler, or host-related issues */
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//-------------------------------------------------------------------------
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// Manifests for the I/O map:
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//-------------------------------------------------------------------------
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// R/W: Data port (byte) for IntelliPort-II,
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// R/W: Data port (byte or word) for IntelliPort-IIEX
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// Incoming or outgoing data passes through a FIFO, the status of which is
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// available in some of the bits in FIFO_STATUS. This (bidirectional) FIFO is
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// the primary means of transferring data, commands, flow-control, and status
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// information between the host and board.
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//
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#define FIFO_DATA 0
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// Another way of passing information between the board and the host is
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// through "mailboxes". Unlike a FIFO, a mailbox holds only a single byte of
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// data. Writing data to the mailbox causes a status bit to be set, and
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// potentially interrupting the intended receiver. The sender has some way to
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// determine whether the data has been read yet; as soon as it has, it may send
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// more. The mailboxes are handled differently on -II and -IIEX products, as
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// suggested below.
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//------------------------------------------------------------------------------
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// Read: Status Register for IntelliPort-II or -IIEX
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// The presence of any bit set here will cause an interrupt to the host,
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// provided the corresponding bit has been unmasked in the interrupt mask
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// register. Furthermore, interrupts to the host are disabled globally until the
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// loadware selects the irq line to use. With the exception of STN_MR, the bits
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// remain set so long as the associated condition is true.
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//
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#define FIFO_STATUS 2
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// Bit map of status bits which are identical for -II and -IIEX
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//
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#define ST_OUT_FULL 0x40 // Outbound FIFO full
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#define ST_IN_EMPTY 0x20 // Inbound FIFO empty
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#define ST_IN_MAIL 0x04 // Inbound Mailbox full
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// The following exists only on the Intelliport-IIEX, and indicates that the
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// board has not read the last outgoing mailbox data yet. In the IntelliPort-II,
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// the outgoing mailbox may be read back: a zero indicates the board has read
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// the data.
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//
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#define STE_OUT_MAIL 0x80 // Outbound mailbox full (!)
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// The following bits are defined differently for -II and -IIEX boards. Code
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// which relies on these bits will need to be functionally different for the two
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// types of boards and should be generally avoided because of the additional
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// complexity this creates:
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// Bit map of status bits only on -II
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// Fifo has been RESET (cleared when the status register is read). Note that
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// this condition cannot be masked and would always interrupt the host, except
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// that the hardware reset also disables interrupts globally from the board
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// until re-enabled by loadware. This could also arise from the
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// Am4701-supported command to reset the chip, but this command is generally not
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// used here.
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//
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#define STN_MR 0x80
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// See the AMD Am4701 data sheet for details on the following four bits. They
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// are not presently used by Computone drivers.
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//
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#define STN_OUT_AF 0x10 // Outbound FIFO almost full (programmable)
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#define STN_IN_AE 0x08 // Inbound FIFO almost empty (programmable)
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#define STN_BD 0x02 // Inbound byte detected
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#define STN_PE 0x01 // Parity/Framing condition detected
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// Bit-map of status bits only on -IIEX
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//
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#define STE_OUT_HF 0x10 // Outbound FIFO half full
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#define STE_IN_HF 0x08 // Inbound FIFO half full
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#define STE_IN_FULL 0x02 // Inbound FIFO full
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#define STE_OUT_MT 0x01 // Outbound FIFO empty
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//------------------------------------------------------------------------------
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// Intelliport-II -- Write Only: the pointer register.
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// Values are written to this register to select the Am4701 internal register to
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// be accessed on the next operation.
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//
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#define FIFO_PTR 0x02
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// Values for the pointer register
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//
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#define SEL_COMMAND 0x1 // Selects the Am4701 command register
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// Some possible commands:
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//
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#define SEL_CMD_MR 0x80 // Am4701 command to reset the chip
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#define SEL_CMD_SH 0x40 // Am4701 command to map the "other" port into the
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// status register.
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#define SEL_CMD_UNSH 0 // Am4701 command to "unshift": port maps into its
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// own status register.
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#define SEL_MASK 0x2 // Selects the Am4701 interrupt mask register. The
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// interrupt mask register is bit-mapped to match
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// the status register (FIFO_STATUS) except for
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// STN_MR. (See above.)
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#define SEL_BYTE_DET 0x3 // Selects the Am4701 byte-detect register. (Not
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// normally used except in diagnostics.)
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#define SEL_OUTMAIL 0x4 // Selects the outbound mailbox (R/W). Reading back
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// a value of zero indicates that the mailbox has
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// been read by the board and is available for more
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// data./ Writing to the mailbox optionally
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// interrupts the board, depending on the loadware's
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// setting of its interrupt mask register.
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#define SEL_AEAF 0x5 // Selects AE/AF threshold register.
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#define SEL_INMAIL 0x6 // Selects the inbound mailbox (Read)
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//------------------------------------------------------------------------------
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// IntelliPort-IIEX -- Write Only: interrupt mask (and misc flags) register:
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// Unlike IntelliPort-II, bit assignments do NOT match those of the status
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// register.
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//
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#define FIFO_MASK 0x2
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// Mailbox readback select:
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// If set, reads to FIFO_MAIL will read the OUTBOUND mailbox (host to board). If
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// clear (default on reset) reads to FIFO_MAIL will read the INBOUND mailbox.
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// This is the normal situation. The clearing of a mailbox is determined on
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// -IIEX boards by waiting for the STE_OUT_MAIL bit to clear. Readback
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// capability is provided for diagnostic purposes only.
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//
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#define MX_OUTMAIL_RSEL 0x80
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#define MX_IN_MAIL 0x40 // Enables interrupts when incoming mailbox goes
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// full (ST_IN_MAIL set).
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#define MX_IN_FULL 0x20 // Enables interrupts when incoming FIFO goes full
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// (STE_IN_FULL).
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#define MX_IN_MT 0x08 // Enables interrupts when incoming FIFO goes empty
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// (ST_IN_MT).
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#define MX_OUT_FULL 0x04 // Enables interrupts when outgoing FIFO goes full
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// (ST_OUT_FULL).
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#define MX_OUT_MT 0x01 // Enables interrupts when outgoing FIFO goes empty
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// (STE_OUT_MT).
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// Any remaining bits are reserved, and should be written to ZERO for
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// compatibility with future Computone products.
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//------------------------------------------------------------------------------
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// IntelliPort-IIEX: -- These are only 6-bit mailboxes !!! -- 11111100 (low two
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// bits always read back 0).
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// Read: One of the mailboxes, usually Inbound.
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// Inbound Mailbox (MX_OUTMAIL_RSEL = 0)
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// Outbound Mailbox (MX_OUTMAIL_RSEL = 1)
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// Write: Outbound Mailbox
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// For the IntelliPort-II boards, the outbound mailbox is read back to determine
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// whether the board has read the data (0 --> data has been read). For the
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// IntelliPort-IIEX, this is done by reading a status register. To determine
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// whether mailbox is available for more outbound data, use the STE_OUT_MAIL bit
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// in FIFO_STATUS. Moreover, although the Outbound Mailbox can be read back by
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// setting MX_OUTMAIL_RSEL, it is NOT cleared when the board reads it, as is the
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// case with the -II boards. For this reason, FIFO_MAIL is normally used to read
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// the inbound FIFO, and MX_OUTMAIL_RSEL kept clear. (See above for
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// MX_OUTMAIL_RSEL description.)
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//
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#define FIFO_MAIL 0x3
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//------------------------------------------------------------------------------
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// WRITE ONLY: Resets the board. (Data doesn't matter).
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//
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#define FIFO_RESET 0x7
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//------------------------------------------------------------------------------
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// READ ONLY: Will have no effect. (Data is undefined.)
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// Actually, there will be an effect, in that the operation is sure to generate
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// a bus cycle: viz., an I/O byte Read. This fact can be used to enforce short
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// delays when no comparable time constant is available.
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//
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#define FIFO_NOP 0x7
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//------------------------------------------------------------------------------
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// RESET & POWER-ON RESET MESSAGE
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/*------------------------------------------------------------------------------
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RESET:
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The IntelliPort-II and -IIEX boards are reset in three ways: Power-up, channel
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reset, and via a write to the reset register described above. For products using
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the ISA bus, these three sources of reset are equvalent. For MCA and EISA buses,
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the Power-up and channel reset sources cause additional hardware initialization
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which should only occur at system startup time.
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The third type of reset, called a "command reset", is done by writing any data
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to the FIFO_RESET address described above. This resets the on-board processor,
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FIFO, UARTS, and associated hardware.
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This passes control of the board to the bootstrap firmware, which performs a
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Power-On Self Test and which detects its current configuration. For example,
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-IIEX products determine the size of FIFO which has been installed, and the
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number and type of expansion boxes attached.
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This and other information is then written to the FIFO in a 16-byte data block
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to be read by the host. This block is guaranteed to be present within two (2)
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seconds of having received the command reset. The firmware is now ready to
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receive loadware from the host.
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It is good practice to perform a command reset to the board explicitly as part
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of your software initialization. This allows your code to properly restart from
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a soft boot. (Many systems do not issue channel reset on soft boot).
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Because of a hardware reset problem on some of the Cirrus Logic 1400's which are
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used on the product, it is recommended that you reset the board twice, separated
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by an approximately 50 milliseconds delay. (VERY approximately: probably ok to
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be off by a factor of five. The important point is that the first command reset
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in fact generates a reset pulse on the board. This pulse is guaranteed to last
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less than 10 milliseconds. The additional delay ensures the 1400 has had the
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chance to respond sufficiently to the first reset. Why not a longer delay? Much
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more than 50 milliseconds gets to be noticable, but the board would still work.
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Once all 16 bytes of the Power-on Reset Message have been read, the bootstrap
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firmware is ready to receive loadware.
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Note on Power-on Reset Message format:
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The various fields have been designed with future expansion in view.
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Combinations of bitfields and values have been defined which define products
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which may not currently exist. This has been done to allow drivers to anticipate
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the possible introduction of products in a systematic fashion. This is not
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intended to suggest that each potential product is actually under consideration.
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------------------------------------------------------------------------------*/
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//----------------------------------------
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// Format of Power-on Reset Message
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//----------------------------------------
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typedef union _porStr // "por" stands for Power On Reset
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{
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unsigned char c[16]; // array used when considering the message as a
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// string of undifferentiated characters
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struct // Elements used when considering values
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{
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// The first two bytes out of the FIFO are two magic numbers. These are
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// intended to establish that there is indeed a member of the
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// IntelliPort-II(EX) family present. The remaining bytes may be
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// expected // to be valid. When reading the Power-on Reset message,
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// if the magic numbers do not match it is probably best to stop
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// reading immediately. You are certainly not reading our board (unless
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// hardware is faulty), and may in fact be reading some other piece of
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// hardware.
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unsigned char porMagic1; // magic number: first byte == POR_MAGIC_1
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unsigned char porMagic2; // magic number: second byte == POR_MAGIC_2
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// The Version, Revision, and Subrevision are stored as absolute numbers
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// and would normally be displayed in the format V.R.S (e.g. 1.0.2)
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unsigned char porVersion; // Bootstrap firmware version number
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unsigned char porRevision; // Bootstrap firmware revision number
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unsigned char porSubRev; // Bootstrap firmware sub-revision number
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unsigned char porID; // Product ID: Bit-mapped according to
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// conventions described below. Among other
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// things, this allows us to distinguish
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// IntelliPort-II boards from IntelliPort-IIEX
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// boards.
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unsigned char porBus; // IntelliPort-II: Unused
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// IntelliPort-IIEX: Bus Information:
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// Bit-mapped below
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unsigned char porMemory; // On-board DRAM size: in 32k blocks
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// porPorts1 (and porPorts2) are used to determine the ports which are
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// available to the board. For non-expandable product, a single number
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// is sufficient. For expandable product, the board may be connected
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// to as many as four boxes. Each box may be (so far) either a 16-port
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// or an 8-port size. Whenever an 8-port box is used, the remaining 8
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// ports leave gaps between existing channels. For that reason,
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// expandable products must report a MAP of available channels. Since
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// each UART supports four ports, we represent each UART found by a
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// single bit. Using two bytes to supply the mapping information we
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// report the presense or absense of up to 16 UARTS, or 64 ports in
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// steps of 4 ports. For -IIEX products, the ports are numbered
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// starting at the box closest to the controller in the "chain".
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// Interpreted Differently for IntelliPort-II and -IIEX.
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// -II: Number of ports (Derived actually from product ID). See
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// Diag1&2 to indicate if uart was actually detected.
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// -IIEX: Bit-map of UARTS found, LSB (see below for MSB of this). This
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// bitmap is based on detecting the uarts themselves;
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// see porFlags for information from the box i.d's.
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unsigned char porPorts1;
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unsigned char porDiag1; // Results of on-board P.O.S.T, 1st byte
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unsigned char porDiag2; // Results of on-board P.O.S.T, 2nd byte
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unsigned char porSpeed; // Speed of local CPU: given as MHz x10
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// e.g., 16.0 MHz CPU is reported as 160
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unsigned char porFlags; // Misc information (see manifests below)
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// Bit-mapped: CPU type, UART's present
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unsigned char porPorts2; // -II: Undefined
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// -IIEX: Bit-map of UARTS found, MSB (see
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// above for LSB)
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// IntelliPort-II: undefined
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// IntelliPort-IIEX: 1 << porFifoSize gives the size, in bytes, of the
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// host interface FIFO, in each direction. When running the -IIEX in
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// 8-bit mode, fifo capacity is halved. The bootstrap firmware will
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// have already accounted for this fact in generating this number.
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unsigned char porFifoSize;
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// IntelliPort-II: undefined
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// IntelliPort-IIEX: The number of boxes connected. (Presently 1-4)
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unsigned char porNumBoxes;
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} e;
|
|
} porStr, *porStrPtr;
|
|
|
|
//--------------------------
|
|
// Values for porStr fields
|
|
//--------------------------
|
|
|
|
//---------------------
|
|
// porMagic1, porMagic2
|
|
//----------------------
|
|
//
|
|
#define POR_MAGIC_1 0x96 // The only valid value for porMagic1
|
|
#define POR_MAGIC_2 0x35 // The only valid value for porMagic2
|
|
#define POR_1_INDEX 0 // Byte position of POR_MAGIC_1
|
|
#define POR_2_INDEX 1 // Ditto for POR_MAGIC_2
|
|
|
|
//----------------------
|
|
// porID
|
|
//----------------------
|
|
//
|
|
#define POR_ID_FAMILY 0xc0 // These bits indicate the general family of
|
|
// product.
|
|
#define POR_ID_FII 0x00 // Family is "IntelliPort-II"
|
|
#define POR_ID_FIIEX 0x40 // Family is "IntelliPort-IIEX"
|
|
|
|
// These bits are reserved, presently zero. May be used at a later date to
|
|
// convey other product information.
|
|
//
|
|
#define POR_ID_RESERVED 0x3c
|
|
|
|
#define POR_ID_SIZE 0x03 // Remaining bits indicate number of ports &
|
|
// Connector information.
|
|
#define POR_ID_II_8 0x00 // For IntelliPort-II, indicates 8-port using
|
|
// standard brick.
|
|
#define POR_ID_II_8R 0x01 // For IntelliPort-II, indicates 8-port using
|
|
// RJ11's (no CTS)
|
|
#define POR_ID_II_6 0x02 // For IntelliPort-II, indicates 6-port using
|
|
// RJ45's
|
|
#define POR_ID_II_4 0x03 // For IntelliPort-II, indicates 4-port using
|
|
// 4xRJ45 connectors
|
|
#define POR_ID_EX 0x00 // For IntelliPort-IIEX, indicates standard
|
|
// expandable controller (other values reserved)
|
|
|
|
//----------------------
|
|
// porBus
|
|
//----------------------
|
|
|
|
// IntelliPort-IIEX only: Board is installed in a 16-bit slot
|
|
//
|
|
#define POR_BUS_SLOT16 0x20
|
|
|
|
// IntelliPort-IIEX only: DIP switch #8 is on, selecting 16-bit host interface
|
|
// operation.
|
|
//
|
|
#define POR_BUS_DIP16 0x10
|
|
|
|
// Bits 0-2 indicate type of bus: This information is stored in the bootstrap
|
|
// loadware, different loadware being used on different products for different
|
|
// buses. For most situations, the drivers do not need this information; but it
|
|
// is handy in a diagnostic environment. For example, on microchannel boards,
|
|
// you would not want to try to test several interrupts, only the one for which
|
|
// you were configured.
|
|
//
|
|
#define POR_BUS_TYPE 0x07
|
|
|
|
// Unknown: this product doesn't know what bus it is running in. (e.g. if same
|
|
// bootstrap firmware were wanted for two different buses.)
|
|
//
|
|
#define POR_BUS_T_UNK 0
|
|
|
|
// Note: existing firmware for ISA-8 and MC-8 currently report the POR_BUS_T_UNK
|
|
// state, since the same bootstrap firmware is used for each.
|
|
|
|
#define POR_BUS_T_MCA 1 // MCA BUS */
|
|
#define POR_BUS_T_EISA 2 // EISA BUS */
|
|
#define POR_BUS_T_ISA 3 // ISA BUS */
|
|
|
|
// Values 4-7 Reserved
|
|
|
|
// Remaining bits are reserved
|
|
|
|
//----------------------
|
|
// porDiag1
|
|
//----------------------
|
|
|
|
#define POR_BAD_MAPPER 0x80 // HW failure on P.O.S.T: Chip mapper failed
|
|
|
|
// These two bits valid only for the IntelliPort-II
|
|
//
|
|
#define POR_BAD_UART1 0x01 // First 1400 bad
|
|
#define POR_BAD_UART2 0x02 // Second 1400 bad
|
|
|
|
//----------------------
|
|
// porDiag2
|
|
//----------------------
|
|
|
|
#define POR_DEBUG_PORT 0x80 // debug port was detected by the P.O.S.T
|
|
#define POR_DIAG_OK 0x00 // Indicates passage: Failure codes not yet
|
|
// available.
|
|
// Other bits undefined.
|
|
//----------------------
|
|
// porFlags
|
|
//----------------------
|
|
|
|
#define POR_CPU 0x03 // These bits indicate supposed CPU type
|
|
#define POR_CPU_8 0x01 // Board uses an 80188 (no such thing yet)
|
|
#define POR_CPU_6 0x02 // Board uses an 80186 (all existing products)
|
|
#define POR_CEX4 0x04 // If set, this is an ISA-CEX/4: An ISA-4 (asic)
|
|
// which is architected like an ISA-CEX connected
|
|
// to a (hitherto impossible) 4-port box.
|
|
#define POR_BOXES 0xf0 // Valid for IntelliPort-IIEX only: Map of Box
|
|
// sizes based on box I.D.
|
|
#define POR_BOX_16 0x10 // Set indicates 16-port, clear 8-port
|
|
|
|
//-------------------------------------
|
|
// LOADWARE and DOWNLOADING CODE
|
|
//-------------------------------------
|
|
|
|
/*
|
|
Loadware may be sent to the board in two ways:
|
|
1) It may be read from a (binary image) data file block by block as each block
|
|
is sent to the board. This is only possible when the initialization is
|
|
performed by code which can access your file system. This is most suitable
|
|
for diagnostics and appications which use the interface library directly.
|
|
|
|
2) It may be hard-coded into your source by including a .h file (typically
|
|
supplied by Computone), which declares a data array and initializes every
|
|
element. This acheives the same result as if an entire loadware file had
|
|
been read into the array.
|
|
|
|
This requires more data space in your program, but access to the file system
|
|
is not required. This method is more suited to driver code, which typically
|
|
is running at a level too low to access the file system directly.
|
|
|
|
At present, loadware can only be generated at Computone.
|
|
|
|
All Loadware begins with a header area which has a particular format. This
|
|
includes a magic number which identifies the file as being (purportedly)
|
|
loadware, CRC (for the loader), and version information.
|
|
*/
|
|
|
|
|
|
//-----------------------------------------------------------------------------
|
|
// Format of loadware block
|
|
//
|
|
// This is defined as a union so we can pass a pointer to one of these items
|
|
// and (if it is the first block) pick out the version information, etc.
|
|
//
|
|
// Otherwise, to deal with this as a simple character array
|
|
//------------------------------------------------------------------------------
|
|
|
|
#define LOADWARE_BLOCK_SIZE 512 // Number of bytes in each block of loadware
|
|
|
|
typedef union _loadHdrStr
|
|
{
|
|
unsigned char c[LOADWARE_BLOCK_SIZE]; // Valid for every block
|
|
|
|
struct // These fields are valid for only the first block of loadware.
|
|
{
|
|
unsigned char loadMagic; // Magic number: see below
|
|
unsigned char loadBlocksMore; // How many more blocks?
|
|
unsigned char loadCRC[2]; // Two CRC bytes: used by loader
|
|
unsigned char loadVersion; // Version number
|
|
unsigned char loadRevision; // Revision number
|
|
unsigned char loadSubRevision; // Sub-revision number
|
|
unsigned char loadSpares[9]; // Presently unused
|
|
unsigned char loadDates[32]; // Null-terminated string which can give
|
|
// date and time of compilation
|
|
} e;
|
|
} loadHdrStr, *loadHdrStrPtr;
|
|
|
|
//------------------------------------
|
|
// Defines for downloading code:
|
|
//------------------------------------
|
|
|
|
// The loadMagic field in the first block of the loadfile must be this, else the
|
|
// file is not valid.
|
|
//
|
|
#define MAGIC_LOADFILE 0x3c
|
|
|
|
// How do we know the load was successful? On completion of the load, the
|
|
// bootstrap firmware returns a code to indicate whether it thought the download
|
|
// was valid and intends to execute it. These are the only possible valid codes:
|
|
//
|
|
#define LOADWARE_OK 0xc3 // Download was ok
|
|
#define LOADWARE_BAD 0x5a // Download was bad (CRC error)
|
|
|
|
// Constants applicable to writing blocks of loadware:
|
|
// The first block of loadware might take 600 mS to load, in extreme cases.
|
|
// (Expandable board: worst case for sending startup messages to the LCD's).
|
|
// The 600mS figure is not really a calculation, but a conservative
|
|
// guess/guarantee. Usually this will be within 100 mS, like subsequent blocks.
|
|
//
|
|
#define MAX_DLOAD_START_TIME 1000 // 1000 mS
|
|
#define MAX_DLOAD_READ_TIME 100 // 100 mS
|
|
|
|
// Firmware should respond with status (see above) within this long of host
|
|
// having sent the final block.
|
|
//
|
|
#define MAX_DLOAD_ACK_TIME 100 // 100 mS, again!
|
|
|
|
//------------------------------------------------------
|
|
// MAXIMUM NUMBER OF PORTS PER BOARD:
|
|
// This is fixed for now (with the expandable), but may
|
|
// be expanding according to even newer products.
|
|
//------------------------------------------------------
|
|
//
|
|
#define ABS_MAX_BOXES 4 // Absolute most boxes per board
|
|
#define ABS_BIGGEST_BOX 16 // Absolute the most ports per box
|
|
#define ABS_MOST_PORTS (ABS_MAX_BOXES * ABS_BIGGEST_BOX)
|
|
|
|
#endif // I2HW_H
|
|
|