1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
112 lines
3.5 KiB
C
112 lines
3.5 KiB
C
/*
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* include/asm-v850/rte_nb85e_cb.h -- Midas labs RTE-V850/NB85E-CB board
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_RTE_NB85E_CB_H__
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#define __V850_RTE_NB85E_CB_H__
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#include <asm/rte_cb.h> /* Common defs for Midas RTE-CB boards. */
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#define PLATFORM "rte-v850e/nb85e-cb"
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#define PLATFORM_LONG "Midas lab RTE-V850E/NB85E-CB"
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#define CPU_CLOCK_FREQ 50000000 /* 50MHz */
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/* 1MB of onboard SRAM. Note that the monitor ROM uses parts of this
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for its own purposes, so care must be taken. */
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#define SRAM_ADDR 0x03C00000
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#define SRAM_SIZE 0x00100000 /* 1MB */
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/* 16MB of onbard SDRAM. */
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#define SDRAM_ADDR 0x01000000
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#define SDRAM_SIZE 0x01000000 /* 16MB */
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/* CPU addresses of GBUS memory spaces. */
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#define GCS0_ADDR 0x00400000 /* GCS0 - Common SRAM (2MB) */
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#define GCS0_SIZE 0x00400000 /* 4MB */
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#define GCS1_ADDR 0x02000000 /* GCS1 - Flash ROM (8MB) */
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#define GCS1_SIZE 0x00800000 /* 8MB */
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#define GCS2_ADDR 0x03900000 /* GCS2 - I/O registers */
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#define GCS2_SIZE 0x00080000 /* 512KB */
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#define GCS3_ADDR 0x02800000 /* GCS3 - EXT-bus: memory space */
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#define GCS3_SIZE 0x00800000 /* 8MB */
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#define GCS4_ADDR 0x03A00000 /* GCS4 - EXT-bus: I/O space */
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#define GCS4_SIZE 0x00200000 /* 2MB */
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#define GCS5_ADDR 0x00800000 /* GCS5 - PCI bus space */
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#define GCS5_SIZE 0x00800000 /* 8MB */
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#define GCS6_ADDR 0x03980000 /* GCS6 - PCI control registers */
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#define GCS6_SIZE 0x00010000 /* 64KB */
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/* The GBUS GINT0 - GINT3 interrupts are connected to CPU interrupts 10-12.
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These are shared among the GBUS interrupts. */
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#define IRQ_GINT(n) (10 + (n))
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#define IRQ_GINT_NUM 3
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/* Used by <asm/rte_cb.h> to derive NUM_MACH_IRQS. */
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#define NUM_RTE_CB_IRQS NUM_CPU_IRQS
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#ifdef CONFIG_ROM_KERNEL
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/* Kernel is in ROM, starting at address 0. */
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#define INTV_BASE 0
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#else /* !CONFIG_ROM_KERNEL */
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/* We're using the ROM monitor. */
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/* The chip's real interrupt vectors are in ROM, but they jump to a
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secondary interrupt vector table in RAM. */
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#define INTV_BASE 0x03CF8000
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/* Scratch memory used by the ROM monitor, which shouldn't be used by
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linux (except for the alternate interrupt vector area, defined
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above). */
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#define MON_SCRATCH_ADDR 0x03CE8000
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#define MON_SCRATCH_SIZE 0x00018000 /* 96KB */
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#endif /* CONFIG_ROM_KERNEL */
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/* Some misc. on-board devices. */
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/* Seven-segment LED display (two digits). Write-only. */
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#define LED_ADDR(n) (0x03802000 + (n))
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#define LED(n) (*(volatile unsigned char *)LED_ADDR(n))
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#define LED_NUM_DIGITS 4
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/* Override the basic TEG UART pre-initialization so that we can
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initialize extra stuff. */
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#undef V850E_UART_PRE_CONFIGURE /* should be defined by <asm/teg.h> */
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#define V850E_UART_PRE_CONFIGURE rte_nb85e_cb_uart_pre_configure
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#ifndef __ASSEMBLY__
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extern void rte_nb85e_cb_uart_pre_configure (unsigned chan,
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unsigned cflags, unsigned baud);
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#endif
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/* This board supports RTS/CTS for the on-chip UART. */
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/* CTS is pin P00. */
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#define V850E_UART_CTS(chan) (! (TEG_PORT0_IO & 0x1))
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/* RTS is pin P02. */
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#define V850E_UART_SET_RTS(chan, val) \
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do { \
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unsigned old = TEG_PORT0_IO; \
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TEG_PORT0_IO = val ? (old & ~0x4) : (old | 0x4); \
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} while (0)
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#endif /* __V850_RTE_NB85E_CB_H__ */
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