9307cacad0
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
752 lines
18 KiB
C
752 lines
18 KiB
C
#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <linux/module.h>
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#include <linux/percpu.h>
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#include <linux/bootmem.h>
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#include <asm/semaphore.h>
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#include <asm/processor.h>
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#include <asm/i387.h>
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#include <asm/msr.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <asm/mtrr.h>
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#include <asm/mce.h>
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/mpspec.h>
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#include <asm/apic.h>
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#include <mach_apic.h>
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#endif
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#include "cpu.h"
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DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
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[GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
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[GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
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[GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
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[GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
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/*
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* Segments used for calling PnP BIOS have byte granularity.
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* They code segments and data segments have fixed 64k limits,
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* the transfer segment sizes are set at run time.
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*/
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/* 32-bit code */
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[GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
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/* 16-bit code */
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[GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
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/* 16-bit data */
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[GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
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/* 16-bit data */
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[GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
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/* 16-bit data */
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[GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
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/*
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* The APM segments have byte granularity and their bases
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* are set at run time. All have 64k limits.
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*/
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/* 32-bit code */
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[GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
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/* 16-bit code */
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[GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
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/* data */
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[GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
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[GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
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[GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
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} };
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EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
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__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
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static int cachesize_override __cpuinitdata = -1;
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static int disable_x86_serial_nr __cpuinitdata = 1;
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struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
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static void __cpuinit default_init(struct cpuinfo_x86 *c)
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{
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/* Not much we can do here... */
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/* Check if at least it has cpuid */
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if (c->cpuid_level == -1) {
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/* No cpuid. It must be an ancient CPU */
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if (c->x86 == 4)
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strcpy(c->x86_model_id, "486");
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else if (c->x86 == 3)
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strcpy(c->x86_model_id, "386");
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}
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}
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static struct cpu_dev __cpuinitdata default_cpu = {
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.c_init = default_init,
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.c_vendor = "Unknown",
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};
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static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
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static int __init cachesize_setup(char *str)
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{
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get_option(&str, &cachesize_override);
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return 1;
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}
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__setup("cachesize=", cachesize_setup);
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int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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{
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unsigned int *v;
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char *p, *q;
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if (cpuid_eax(0x80000000) < 0x80000004)
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return 0;
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v = (unsigned int *) c->x86_model_id;
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cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
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cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
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cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
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c->x86_model_id[48] = 0;
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/* Intel chips right-justify this string for some dumb reason;
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undo that brain damage */
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p = q = &c->x86_model_id[0];
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while (*p == ' ')
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p++;
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if (p != q) {
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while (*p)
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*q++ = *p++;
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while (q <= &c->x86_model_id[48])
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*q++ = '\0'; /* Zero-pad the rest */
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}
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return 1;
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}
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void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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{
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unsigned int n, dummy, ecx, edx, l2size;
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n = cpuid_eax(0x80000000);
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if (n >= 0x80000005) {
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cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
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printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
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edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
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c->x86_cache_size = (ecx>>24)+(edx>>24);
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}
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if (n < 0x80000006) /* Some chips just has a large L1. */
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return;
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ecx = cpuid_ecx(0x80000006);
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l2size = ecx >> 16;
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/* do processor-specific cache resizing */
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if (this_cpu->c_size_cache)
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l2size = this_cpu->c_size_cache(c, l2size);
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/* Allow user to override all this if necessary. */
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if (cachesize_override != -1)
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l2size = cachesize_override;
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if (l2size == 0)
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return; /* Again, no L2 cache is possible */
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c->x86_cache_size = l2size;
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printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
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l2size, ecx & 0xFF);
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}
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/*
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* Naming convention should be: <Name> [(<Codename>)]
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* This table only is used unless init_<vendor>() below doesn't set it;
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* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
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*
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*/
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/* Look up CPU names by table lookup. */
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static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
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{
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struct cpu_model_info *info;
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if (c->x86_model >= 16)
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return NULL; /* Range check */
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if (!this_cpu)
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return NULL;
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info = this_cpu->c_models;
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while (info && info->family) {
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if (info->family == c->x86)
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return info->model_names[c->x86_model];
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info++;
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}
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return NULL; /* Not found */
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}
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static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
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{
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char *v = c->x86_vendor_id;
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int i;
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static int printed;
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for (i = 0; i < X86_VENDOR_NUM; i++) {
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if (cpu_devs[i]) {
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if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
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(cpu_devs[i]->c_ident[1] &&
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!strcmp(v, cpu_devs[i]->c_ident[1]))) {
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c->x86_vendor = i;
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if (!early)
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this_cpu = cpu_devs[i];
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return;
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}
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}
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}
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if (!printed) {
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printed++;
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printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
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printk(KERN_ERR "CPU: Your system may be unstable.\n");
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}
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c->x86_vendor = X86_VENDOR_UNKNOWN;
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this_cpu = &default_cpu;
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}
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static int __init x86_fxsr_setup(char *s)
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{
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setup_clear_cpu_cap(X86_FEATURE_FXSR);
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setup_clear_cpu_cap(X86_FEATURE_XMM);
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return 1;
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}
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__setup("nofxsr", x86_fxsr_setup);
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static int __init x86_sep_setup(char *s)
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{
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setup_clear_cpu_cap(X86_FEATURE_SEP);
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return 1;
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}
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__setup("nosep", x86_sep_setup);
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(u32 flag)
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{
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u32 f1, f2;
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asm("pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl\n\t"
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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return ((f1^f2) & flag) != 0;
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}
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/* Probe for the CPUID instruction */
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static int __cpuinit have_cpuid_p(void)
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{
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
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void __init cpu_detect(struct cpuinfo_x86 *c)
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{
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/* Get vendor name */
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cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
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(unsigned int *)&c->x86_vendor_id[0],
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(unsigned int *)&c->x86_vendor_id[8],
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(unsigned int *)&c->x86_vendor_id[4]);
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c->x86 = 4;
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if (c->cpuid_level >= 0x00000001) {
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u32 junk, tfms, cap0, misc;
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cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
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c->x86 = (tfms >> 8) & 15;
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c->x86_model = (tfms >> 4) & 15;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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c->x86_mask = tfms & 15;
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if (cap0 & (1<<19)) {
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c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
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c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
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}
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}
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}
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static void __cpuinit early_get_cap(struct cpuinfo_x86 *c)
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{
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u32 tfms, xlvl;
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unsigned int ebx;
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memset(&c->x86_capability, 0, sizeof c->x86_capability);
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if (have_cpuid_p()) {
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/* Intel-defined flags: level 0x00000001 */
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if (c->cpuid_level >= 0x00000001) {
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u32 capability, excap;
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cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
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c->x86_capability[0] = capability;
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c->x86_capability[4] = excap;
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}
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/* AMD-defined flags: level 0x80000001 */
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xlvl = cpuid_eax(0x80000000);
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if ((xlvl & 0xffff0000) == 0x80000000) {
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if (xlvl >= 0x80000001) {
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c->x86_capability[1] = cpuid_edx(0x80000001);
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c->x86_capability[6] = cpuid_ecx(0x80000001);
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}
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}
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}
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clear_cpu_cap(c, X86_FEATURE_PAT);
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switch (c->x86_vendor) {
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case X86_VENDOR_AMD:
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if (c->x86 >= 0xf && c->x86 <= 0x11)
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set_cpu_cap(c, X86_FEATURE_PAT);
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break;
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case X86_VENDOR_INTEL:
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if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
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set_cpu_cap(c, X86_FEATURE_PAT);
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break;
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}
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}
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/*
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* Do minimum CPU detection early.
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* Fields really needed: vendor, cpuid_level, family, model, mask,
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* cache alignment.
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* The others are not touched to avoid unwanted side effects.
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*
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* WARNING: this function is only called on the BP. Don't add code here
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* that is supposed to run on all CPUs.
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*/
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static void __init early_cpu_detect(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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c->x86_cache_alignment = 32;
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c->x86_clflush_size = 32;
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if (!have_cpuid_p())
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return;
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cpu_detect(c);
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get_cpu_vendor(c, 1);
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if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
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cpu_devs[c->x86_vendor]->c_early_init)
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cpu_devs[c->x86_vendor]->c_early_init(c);
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early_get_cap(c);
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}
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static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
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{
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u32 tfms, xlvl;
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unsigned int ebx;
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if (have_cpuid_p()) {
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/* Get vendor name */
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cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
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(unsigned int *)&c->x86_vendor_id[0],
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(unsigned int *)&c->x86_vendor_id[8],
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(unsigned int *)&c->x86_vendor_id[4]);
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get_cpu_vendor(c, 0);
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/* Initialize the standard set of capabilities */
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/* Note that the vendor-specific code below might override */
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/* Intel-defined flags: level 0x00000001 */
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if (c->cpuid_level >= 0x00000001) {
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u32 capability, excap;
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cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
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c->x86_capability[0] = capability;
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c->x86_capability[4] = excap;
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c->x86 = (tfms >> 8) & 15;
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c->x86_model = (tfms >> 4) & 15;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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c->x86_mask = tfms & 15;
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c->initial_apicid = (ebx >> 24) & 0xFF;
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#ifdef CONFIG_X86_HT
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c->apicid = phys_pkg_id(c->initial_apicid, 0);
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c->phys_proc_id = c->initial_apicid;
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#else
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c->apicid = c->initial_apicid;
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#endif
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if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
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c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
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} else {
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/* Have CPUID level 0 only - unheard of */
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c->x86 = 4;
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}
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/* AMD-defined flags: level 0x80000001 */
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xlvl = cpuid_eax(0x80000000);
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if ((xlvl & 0xffff0000) == 0x80000000) {
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if (xlvl >= 0x80000001) {
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c->x86_capability[1] = cpuid_edx(0x80000001);
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c->x86_capability[6] = cpuid_ecx(0x80000001);
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}
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if (xlvl >= 0x80000004)
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get_model_name(c); /* Default name */
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}
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init_scattered_cpuid_features(c);
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}
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clear_cpu_cap(c, X86_FEATURE_PAT);
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switch (c->x86_vendor) {
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case X86_VENDOR_AMD:
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if (c->x86 >= 0xf && c->x86 <= 0x11)
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set_cpu_cap(c, X86_FEATURE_PAT);
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break;
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case X86_VENDOR_INTEL:
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if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
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set_cpu_cap(c, X86_FEATURE_PAT);
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break;
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}
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}
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static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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{
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if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
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/* Disable processor serial number */
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unsigned long lo, hi;
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rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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lo |= 0x200000;
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wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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printk(KERN_NOTICE "CPU serial number disabled.\n");
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clear_cpu_cap(c, X86_FEATURE_PN);
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/* Disabling the serial number may affect the cpuid level */
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c->cpuid_level = cpuid_eax(0);
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}
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}
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static int __init x86_serial_nr_setup(char *s)
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{
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disable_x86_serial_nr = 0;
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return 1;
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}
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__setup("serialnumber", x86_serial_nr_setup);
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/*
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* This does the hard work of actually picking apart the CPU stuff...
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*/
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void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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{
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int i;
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c->loops_per_jiffy = loops_per_jiffy;
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c->x86_cache_size = -1;
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c->x86_vendor = X86_VENDOR_UNKNOWN;
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c->cpuid_level = -1; /* CPUID not detected */
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c->x86_model = c->x86_mask = 0; /* So far unknown... */
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c->x86_vendor_id[0] = '\0'; /* Unset */
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c->x86_model_id[0] = '\0'; /* Unset */
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c->x86_max_cores = 1;
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c->x86_clflush_size = 32;
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memset(&c->x86_capability, 0, sizeof c->x86_capability);
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if (!have_cpuid_p()) {
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|
/*
|
|
* First of all, decide if this is a 486 or higher
|
|
* It's a 486 if we can modify the AC flag
|
|
*/
|
|
if (flag_is_changeable_p(X86_EFLAGS_AC))
|
|
c->x86 = 4;
|
|
else
|
|
c->x86 = 3;
|
|
}
|
|
|
|
generic_identify(c);
|
|
|
|
if (this_cpu->c_identify)
|
|
this_cpu->c_identify(c);
|
|
|
|
/*
|
|
* Vendor-specific initialization. In this section we
|
|
* canonicalize the feature flags, meaning if there are
|
|
* features a certain CPU supports which CPUID doesn't
|
|
* tell us, CPUID claiming incorrect flags, or other bugs,
|
|
* we handle them here.
|
|
*
|
|
* At the end of this section, c->x86_capability better
|
|
* indicate the features this CPU genuinely supports!
|
|
*/
|
|
if (this_cpu->c_init)
|
|
this_cpu->c_init(c);
|
|
|
|
/* Disable the PN if appropriate */
|
|
squash_the_stupid_serial_number(c);
|
|
|
|
/*
|
|
* The vendor-specific functions might have changed features. Now
|
|
* we do "generic changes."
|
|
*/
|
|
|
|
/* If the model name is still unset, do table lookup. */
|
|
if (!c->x86_model_id[0]) {
|
|
char *p;
|
|
p = table_lookup_model(c);
|
|
if (p)
|
|
strcpy(c->x86_model_id, p);
|
|
else
|
|
/* Last resort... */
|
|
sprintf(c->x86_model_id, "%02x/%02x",
|
|
c->x86, c->x86_model);
|
|
}
|
|
|
|
/*
|
|
* On SMP, boot_cpu_data holds the common feature set between
|
|
* all CPUs; so make sure that we indicate which features are
|
|
* common between the CPUs. The first time this routine gets
|
|
* executed, c == &boot_cpu_data.
|
|
*/
|
|
if (c != &boot_cpu_data) {
|
|
/* AND the already accumulated flags with these */
|
|
for (i = 0 ; i < NCAPINTS ; i++)
|
|
boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
|
|
}
|
|
|
|
/* Clear all flags overriden by options */
|
|
for (i = 0; i < NCAPINTS; i++)
|
|
c->x86_capability[i] &= ~cleared_cpu_caps[i];
|
|
|
|
/* Init Machine Check Exception if available. */
|
|
mcheck_init(c);
|
|
|
|
select_idle_routine(c);
|
|
}
|
|
|
|
void __init identify_boot_cpu(void)
|
|
{
|
|
identify_cpu(&boot_cpu_data);
|
|
sysenter_setup();
|
|
enable_sep_cpu();
|
|
}
|
|
|
|
void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
|
|
{
|
|
BUG_ON(c == &boot_cpu_data);
|
|
identify_cpu(c);
|
|
enable_sep_cpu();
|
|
mtrr_ap_init();
|
|
}
|
|
|
|
#ifdef CONFIG_X86_HT
|
|
void __cpuinit detect_ht(struct cpuinfo_x86 *c)
|
|
{
|
|
u32 eax, ebx, ecx, edx;
|
|
int index_msb, core_bits;
|
|
|
|
cpuid(1, &eax, &ebx, &ecx, &edx);
|
|
|
|
if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
|
|
return;
|
|
|
|
smp_num_siblings = (ebx & 0xff0000) >> 16;
|
|
|
|
if (smp_num_siblings == 1) {
|
|
printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
|
|
} else if (smp_num_siblings > 1) {
|
|
|
|
if (smp_num_siblings > NR_CPUS) {
|
|
printk(KERN_WARNING "CPU: Unsupported number of the "
|
|
"siblings %d", smp_num_siblings);
|
|
smp_num_siblings = 1;
|
|
return;
|
|
}
|
|
|
|
index_msb = get_count_order(smp_num_siblings);
|
|
c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
|
|
|
|
printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
|
|
c->phys_proc_id);
|
|
|
|
smp_num_siblings = smp_num_siblings / c->x86_max_cores;
|
|
|
|
index_msb = get_count_order(smp_num_siblings) ;
|
|
|
|
core_bits = get_count_order(c->x86_max_cores);
|
|
|
|
c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
|
|
((1 << core_bits) - 1);
|
|
|
|
if (c->x86_max_cores > 1)
|
|
printk(KERN_INFO "CPU: Processor Core ID: %d\n",
|
|
c->cpu_core_id);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static __init int setup_noclflush(char *arg)
|
|
{
|
|
setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
|
|
return 1;
|
|
}
|
|
__setup("noclflush", setup_noclflush);
|
|
|
|
void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
|
|
{
|
|
char *vendor = NULL;
|
|
|
|
if (c->x86_vendor < X86_VENDOR_NUM)
|
|
vendor = this_cpu->c_vendor;
|
|
else if (c->cpuid_level >= 0)
|
|
vendor = c->x86_vendor_id;
|
|
|
|
if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
|
|
printk("%s ", vendor);
|
|
|
|
if (!c->x86_model_id[0])
|
|
printk("%d86", c->x86);
|
|
else
|
|
printk("%s", c->x86_model_id);
|
|
|
|
if (c->x86_mask || c->cpuid_level >= 0)
|
|
printk(" stepping %02x\n", c->x86_mask);
|
|
else
|
|
printk("\n");
|
|
}
|
|
|
|
static __init int setup_disablecpuid(char *arg)
|
|
{
|
|
int bit;
|
|
if (get_option(&arg, &bit) && bit < NCAPINTS*32)
|
|
setup_clear_cpu_cap(bit);
|
|
else
|
|
return 0;
|
|
return 1;
|
|
}
|
|
__setup("clearcpuid=", setup_disablecpuid);
|
|
|
|
cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
|
|
|
|
void __init early_cpu_init(void)
|
|
{
|
|
struct cpu_vendor_dev *cvdev;
|
|
|
|
for (cvdev = __x86cpuvendor_start ;
|
|
cvdev < __x86cpuvendor_end ;
|
|
cvdev++)
|
|
cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
|
|
|
|
early_cpu_detect();
|
|
}
|
|
|
|
/* Make sure %fs is initialized properly in idle threads */
|
|
struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
|
|
{
|
|
memset(regs, 0, sizeof(struct pt_regs));
|
|
regs->fs = __KERNEL_PERCPU;
|
|
return regs;
|
|
}
|
|
|
|
/* Current gdt points %fs at the "master" per-cpu area: after this,
|
|
* it's on the real one. */
|
|
void switch_to_new_gdt(void)
|
|
{
|
|
struct desc_ptr gdt_descr;
|
|
|
|
gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
|
|
gdt_descr.size = GDT_SIZE - 1;
|
|
load_gdt(&gdt_descr);
|
|
asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
|
|
}
|
|
|
|
/*
|
|
* cpu_init() initializes state that is per-CPU. Some data is already
|
|
* initialized (naturally) in the bootstrap process, such as the GDT
|
|
* and IDT. We reload them nevertheless, this function acts as a
|
|
* 'CPU state barrier', nothing should get across.
|
|
*/
|
|
void __cpuinit cpu_init(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
struct task_struct *curr = current;
|
|
struct tss_struct *t = &per_cpu(init_tss, cpu);
|
|
struct thread_struct *thread = &curr->thread;
|
|
|
|
if (cpu_test_and_set(cpu, cpu_initialized)) {
|
|
printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
|
|
for (;;) local_irq_enable();
|
|
}
|
|
|
|
printk(KERN_INFO "Initializing CPU#%d\n", cpu);
|
|
|
|
if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
|
|
clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
|
|
|
|
load_idt(&idt_descr);
|
|
switch_to_new_gdt();
|
|
|
|
/*
|
|
* Set up and load the per-CPU TSS and LDT
|
|
*/
|
|
atomic_inc(&init_mm.mm_count);
|
|
curr->active_mm = &init_mm;
|
|
if (curr->mm)
|
|
BUG();
|
|
enter_lazy_tlb(&init_mm, curr);
|
|
|
|
load_sp0(t, thread);
|
|
set_tss_desc(cpu, t);
|
|
load_TR_desc();
|
|
load_LDT(&init_mm.context);
|
|
|
|
#ifdef CONFIG_DOUBLEFAULT
|
|
/* Set up doublefault TSS pointer in the GDT */
|
|
__set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
|
|
#endif
|
|
|
|
/* Clear %gs. */
|
|
asm volatile ("mov %0, %%gs" : : "r" (0));
|
|
|
|
/* Clear all 6 debug registers: */
|
|
set_debugreg(0, 0);
|
|
set_debugreg(0, 1);
|
|
set_debugreg(0, 2);
|
|
set_debugreg(0, 3);
|
|
set_debugreg(0, 6);
|
|
set_debugreg(0, 7);
|
|
|
|
/*
|
|
* Force FPU initialization:
|
|
*/
|
|
current_thread_info()->status = 0;
|
|
clear_used_math();
|
|
mxcsr_feature_mask_init();
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
void __cpuinit cpu_uninit(void)
|
|
{
|
|
int cpu = raw_smp_processor_id();
|
|
cpu_clear(cpu, cpu_initialized);
|
|
|
|
/* lazy TLB state */
|
|
per_cpu(cpu_tlbstate, cpu).state = 0;
|
|
per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
|
|
}
|
|
#endif
|