Jack Morgenstein 6e694ea33e IB/mlx4: Fix data corruption triggered by wrong headroom marking order ... This is an addendum to commit 0e6e7416 ("IB/mlx4: Handle new FW requirement for send request prefetching"). We also need to handle prefetch marking properly for S/G segments, or else the HCA may end up processing S/G segments that are not fully written and end up sending the wrong data. This can actually cause data corruption in practice, especially on systems with relatively slow CPUs (where the HCA is more likely to prefetch while the CPU is in the middle of writing a work request into memory). We write S/G segments in reverse order into the WQE, in order to guarantee that the first dword of all cachelines containing S/G segments is written last (overwriting the headroom invalidation pattern). The entire cacheline will thus contain valid data when the invalidation pattern is overwritten. Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>		2007-09-23 13:03:22 -07:00
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ah.c
cq.c	IB/mlx4: Fix opcode returned in RDMA read completion	2007-08-03 14:29:06 -07:00
doorbell.c
Kconfig	IB: Use menuconfig for InfiniBand menu	2007-07-09 20:12:26 -07:00
mad.c	IB/mlx4: Incorrect semicolon after if statement	2007-08-15 20:24:06 -07:00
main.c	IB/mlx4: Implement query SRQ	2007-07-12 15:41:24 -07:00
Makefile
mlx4_ib.h	IB/mlx4: Implement query SRQ	2007-07-12 15:41:24 -07:00
mr.c
qp.c	IB/mlx4: Fix data corruption triggered by wrong headroom marking order	2007-09-23 13:03:22 -07:00
srq.c	IB/mlx4: Implement query SRQ	2007-07-12 15:41:24 -07:00
user.h	IB/mlx4: Handle new FW requirement for send request prefetching	2007-06-18 08:13:48 -07:00