ee43eb788b
The kernel uses SPRG registers for various purposes, typically in low level assembly code as scratch registers or to hold per-cpu global infos such as the PACA or the current thread_info pointer. We want to be able to easily shuffle the usage of those registers as some implementations have specific constraints realted to some of them, for example, some have userspace readable aliases, etc.. and the current choice isn't always the best. This patch should not change any code generation, and replaces the usage of SPRN_SPRGn everywhere in the kernel with a named replacement and adds documentation next to the definition of the names as to what those are used for on each processor family. The only parts that still use the original numbers are bits of KVM or suspend/resume code that just blindly needs to save/restore all the SPRGs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
433 lines
11 KiB
ArmAsm
433 lines
11 KiB
ArmAsm
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright IBM Corp. 2007
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*
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* Authors: Hollis Blanchard <hollisb@us.ibm.com>
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*/
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#include <asm/ppc_asm.h>
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#include <asm/kvm_asm.h>
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#include <asm/reg.h>
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#include <asm/mmu-44x.h>
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#include <asm/page.h>
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#include <asm/asm-offsets.h>
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#define KVMPPC_MSR_MASK (MSR_CE|MSR_EE|MSR_PR|MSR_DE|MSR_ME|MSR_IS|MSR_DS)
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#define VCPU_GPR(n) (VCPU_GPRS + (n * 4))
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/* The host stack layout: */
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#define HOST_R1 0 /* Implied by stwu. */
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#define HOST_CALLEE_LR 4
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#define HOST_RUN 8
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/* r2 is special: it holds 'current', and it made nonvolatile in the
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* kernel with the -ffixed-r2 gcc option. */
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#define HOST_R2 12
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#define HOST_NV_GPRS 16
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#define HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * 4))
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#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + 4)
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#define HOST_STACK_SIZE (((HOST_MIN_STACK_SIZE + 15) / 16) * 16) /* Align. */
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#define HOST_STACK_LR (HOST_STACK_SIZE + 4) /* In caller stack frame. */
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#define NEED_INST_MASK ((1<<BOOKE_INTERRUPT_PROGRAM) | \
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(1<<BOOKE_INTERRUPT_DTLB_MISS) | \
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(1<<BOOKE_INTERRUPT_DEBUG))
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#define NEED_DEAR_MASK ((1<<BOOKE_INTERRUPT_DATA_STORAGE) | \
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(1<<BOOKE_INTERRUPT_DTLB_MISS))
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#define NEED_ESR_MASK ((1<<BOOKE_INTERRUPT_DATA_STORAGE) | \
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(1<<BOOKE_INTERRUPT_INST_STORAGE) | \
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(1<<BOOKE_INTERRUPT_PROGRAM) | \
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(1<<BOOKE_INTERRUPT_DTLB_MISS))
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.macro KVM_HANDLER ivor_nr
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_GLOBAL(kvmppc_handler_\ivor_nr)
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/* Get pointer to vcpu and record exit number. */
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mtspr SPRN_SPRG_WSCRATCH0, r4
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mfspr r4, SPRN_SPRG_RVCPU
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stw r5, VCPU_GPR(r5)(r4)
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stw r6, VCPU_GPR(r6)(r4)
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mfctr r5
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lis r6, kvmppc_resume_host@h
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stw r5, VCPU_CTR(r4)
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li r5, \ivor_nr
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ori r6, r6, kvmppc_resume_host@l
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mtctr r6
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bctr
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.endm
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_GLOBAL(kvmppc_handlers_start)
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KVM_HANDLER BOOKE_INTERRUPT_CRITICAL
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KVM_HANDLER BOOKE_INTERRUPT_MACHINE_CHECK
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KVM_HANDLER BOOKE_INTERRUPT_DATA_STORAGE
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KVM_HANDLER BOOKE_INTERRUPT_INST_STORAGE
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KVM_HANDLER BOOKE_INTERRUPT_EXTERNAL
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KVM_HANDLER BOOKE_INTERRUPT_ALIGNMENT
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KVM_HANDLER BOOKE_INTERRUPT_PROGRAM
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KVM_HANDLER BOOKE_INTERRUPT_FP_UNAVAIL
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KVM_HANDLER BOOKE_INTERRUPT_SYSCALL
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KVM_HANDLER BOOKE_INTERRUPT_AP_UNAVAIL
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KVM_HANDLER BOOKE_INTERRUPT_DECREMENTER
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KVM_HANDLER BOOKE_INTERRUPT_FIT
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KVM_HANDLER BOOKE_INTERRUPT_WATCHDOG
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KVM_HANDLER BOOKE_INTERRUPT_DTLB_MISS
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KVM_HANDLER BOOKE_INTERRUPT_ITLB_MISS
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KVM_HANDLER BOOKE_INTERRUPT_DEBUG
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KVM_HANDLER BOOKE_INTERRUPT_SPE_UNAVAIL
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KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_DATA
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KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_ROUND
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_GLOBAL(kvmppc_handler_len)
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.long kvmppc_handler_1 - kvmppc_handler_0
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/* Registers:
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* SPRG_SCRATCH0: guest r4
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* r4: vcpu pointer
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* r5: KVM exit number
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*/
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_GLOBAL(kvmppc_resume_host)
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stw r3, VCPU_GPR(r3)(r4)
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mfcr r3
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stw r3, VCPU_CR(r4)
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stw r7, VCPU_GPR(r7)(r4)
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stw r8, VCPU_GPR(r8)(r4)
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stw r9, VCPU_GPR(r9)(r4)
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li r6, 1
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slw r6, r6, r5
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#ifdef CONFIG_KVM_EXIT_TIMING
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/* save exit time */
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1:
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mfspr r7, SPRN_TBRU
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mfspr r8, SPRN_TBRL
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mfspr r9, SPRN_TBRU
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cmpw r9, r7
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bne 1b
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stw r8, VCPU_TIMING_EXIT_TBL(r4)
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stw r9, VCPU_TIMING_EXIT_TBU(r4)
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#endif
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/* Save the faulting instruction and all GPRs for emulation. */
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andi. r7, r6, NEED_INST_MASK
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beq ..skip_inst_copy
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mfspr r9, SPRN_SRR0
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mfmsr r8
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ori r7, r8, MSR_DS
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mtmsr r7
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isync
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lwz r9, 0(r9)
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mtmsr r8
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isync
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stw r9, VCPU_LAST_INST(r4)
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stw r15, VCPU_GPR(r15)(r4)
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stw r16, VCPU_GPR(r16)(r4)
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stw r17, VCPU_GPR(r17)(r4)
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stw r18, VCPU_GPR(r18)(r4)
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stw r19, VCPU_GPR(r19)(r4)
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stw r20, VCPU_GPR(r20)(r4)
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stw r21, VCPU_GPR(r21)(r4)
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stw r22, VCPU_GPR(r22)(r4)
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stw r23, VCPU_GPR(r23)(r4)
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stw r24, VCPU_GPR(r24)(r4)
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stw r25, VCPU_GPR(r25)(r4)
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stw r26, VCPU_GPR(r26)(r4)
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stw r27, VCPU_GPR(r27)(r4)
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stw r28, VCPU_GPR(r28)(r4)
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stw r29, VCPU_GPR(r29)(r4)
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stw r30, VCPU_GPR(r30)(r4)
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stw r31, VCPU_GPR(r31)(r4)
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..skip_inst_copy:
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/* Also grab DEAR and ESR before the host can clobber them. */
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andi. r7, r6, NEED_DEAR_MASK
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beq ..skip_dear
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mfspr r9, SPRN_DEAR
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stw r9, VCPU_FAULT_DEAR(r4)
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..skip_dear:
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andi. r7, r6, NEED_ESR_MASK
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beq ..skip_esr
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mfspr r9, SPRN_ESR
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stw r9, VCPU_FAULT_ESR(r4)
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..skip_esr:
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/* Save remaining volatile guest register state to vcpu. */
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stw r0, VCPU_GPR(r0)(r4)
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stw r1, VCPU_GPR(r1)(r4)
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stw r2, VCPU_GPR(r2)(r4)
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stw r10, VCPU_GPR(r10)(r4)
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stw r11, VCPU_GPR(r11)(r4)
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stw r12, VCPU_GPR(r12)(r4)
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stw r13, VCPU_GPR(r13)(r4)
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stw r14, VCPU_GPR(r14)(r4) /* We need a NV GPR below. */
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mflr r3
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stw r3, VCPU_LR(r4)
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mfxer r3
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stw r3, VCPU_XER(r4)
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mfspr r3, SPRN_SPRG_RSCRATCH0
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stw r3, VCPU_GPR(r4)(r4)
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mfspr r3, SPRN_SRR0
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stw r3, VCPU_PC(r4)
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/* Restore host stack pointer and PID before IVPR, since the host
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* exception handlers use them. */
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lwz r1, VCPU_HOST_STACK(r4)
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lwz r3, VCPU_HOST_PID(r4)
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mtspr SPRN_PID, r3
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/* Restore host IVPR before re-enabling interrupts. We cheat and know
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* that Linux IVPR is always 0xc0000000. */
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lis r3, 0xc000
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mtspr SPRN_IVPR, r3
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/* Switch to kernel stack and jump to handler. */
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LOAD_REG_ADDR(r3, kvmppc_handle_exit)
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mtctr r3
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lwz r3, HOST_RUN(r1)
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lwz r2, HOST_R2(r1)
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mr r14, r4 /* Save vcpu pointer. */
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bctrl /* kvmppc_handle_exit() */
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/* Restore vcpu pointer and the nonvolatiles we used. */
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mr r4, r14
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lwz r14, VCPU_GPR(r14)(r4)
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/* Sometimes instruction emulation must restore complete GPR state. */
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andi. r5, r3, RESUME_FLAG_NV
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beq ..skip_nv_load
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lwz r15, VCPU_GPR(r15)(r4)
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lwz r16, VCPU_GPR(r16)(r4)
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lwz r17, VCPU_GPR(r17)(r4)
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lwz r18, VCPU_GPR(r18)(r4)
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lwz r19, VCPU_GPR(r19)(r4)
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lwz r20, VCPU_GPR(r20)(r4)
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lwz r21, VCPU_GPR(r21)(r4)
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lwz r22, VCPU_GPR(r22)(r4)
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lwz r23, VCPU_GPR(r23)(r4)
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lwz r24, VCPU_GPR(r24)(r4)
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lwz r25, VCPU_GPR(r25)(r4)
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lwz r26, VCPU_GPR(r26)(r4)
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lwz r27, VCPU_GPR(r27)(r4)
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lwz r28, VCPU_GPR(r28)(r4)
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lwz r29, VCPU_GPR(r29)(r4)
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lwz r30, VCPU_GPR(r30)(r4)
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lwz r31, VCPU_GPR(r31)(r4)
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..skip_nv_load:
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/* Should we return to the guest? */
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andi. r5, r3, RESUME_FLAG_HOST
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beq lightweight_exit
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srawi r3, r3, 2 /* Shift -ERR back down. */
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heavyweight_exit:
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/* Not returning to guest. */
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/* We already saved guest volatile register state; now save the
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* non-volatiles. */
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stw r15, VCPU_GPR(r15)(r4)
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stw r16, VCPU_GPR(r16)(r4)
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stw r17, VCPU_GPR(r17)(r4)
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stw r18, VCPU_GPR(r18)(r4)
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stw r19, VCPU_GPR(r19)(r4)
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stw r20, VCPU_GPR(r20)(r4)
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stw r21, VCPU_GPR(r21)(r4)
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stw r22, VCPU_GPR(r22)(r4)
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stw r23, VCPU_GPR(r23)(r4)
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stw r24, VCPU_GPR(r24)(r4)
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stw r25, VCPU_GPR(r25)(r4)
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stw r26, VCPU_GPR(r26)(r4)
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stw r27, VCPU_GPR(r27)(r4)
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stw r28, VCPU_GPR(r28)(r4)
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stw r29, VCPU_GPR(r29)(r4)
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stw r30, VCPU_GPR(r30)(r4)
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stw r31, VCPU_GPR(r31)(r4)
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/* Load host non-volatile register state from host stack. */
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lwz r14, HOST_NV_GPR(r14)(r1)
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lwz r15, HOST_NV_GPR(r15)(r1)
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lwz r16, HOST_NV_GPR(r16)(r1)
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lwz r17, HOST_NV_GPR(r17)(r1)
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lwz r18, HOST_NV_GPR(r18)(r1)
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lwz r19, HOST_NV_GPR(r19)(r1)
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lwz r20, HOST_NV_GPR(r20)(r1)
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lwz r21, HOST_NV_GPR(r21)(r1)
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lwz r22, HOST_NV_GPR(r22)(r1)
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lwz r23, HOST_NV_GPR(r23)(r1)
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lwz r24, HOST_NV_GPR(r24)(r1)
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lwz r25, HOST_NV_GPR(r25)(r1)
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lwz r26, HOST_NV_GPR(r26)(r1)
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lwz r27, HOST_NV_GPR(r27)(r1)
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lwz r28, HOST_NV_GPR(r28)(r1)
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lwz r29, HOST_NV_GPR(r29)(r1)
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lwz r30, HOST_NV_GPR(r30)(r1)
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lwz r31, HOST_NV_GPR(r31)(r1)
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/* Return to kvm_vcpu_run(). */
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lwz r4, HOST_STACK_LR(r1)
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addi r1, r1, HOST_STACK_SIZE
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mtlr r4
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/* r3 still contains the return code from kvmppc_handle_exit(). */
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blr
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/* Registers:
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* r3: kvm_run pointer
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* r4: vcpu pointer
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*/
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_GLOBAL(__kvmppc_vcpu_run)
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stwu r1, -HOST_STACK_SIZE(r1)
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stw r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
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/* Save host state to stack. */
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stw r3, HOST_RUN(r1)
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mflr r3
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stw r3, HOST_STACK_LR(r1)
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/* Save host non-volatile register state to stack. */
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stw r14, HOST_NV_GPR(r14)(r1)
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stw r15, HOST_NV_GPR(r15)(r1)
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stw r16, HOST_NV_GPR(r16)(r1)
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stw r17, HOST_NV_GPR(r17)(r1)
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stw r18, HOST_NV_GPR(r18)(r1)
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stw r19, HOST_NV_GPR(r19)(r1)
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stw r20, HOST_NV_GPR(r20)(r1)
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stw r21, HOST_NV_GPR(r21)(r1)
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stw r22, HOST_NV_GPR(r22)(r1)
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stw r23, HOST_NV_GPR(r23)(r1)
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stw r24, HOST_NV_GPR(r24)(r1)
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stw r25, HOST_NV_GPR(r25)(r1)
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stw r26, HOST_NV_GPR(r26)(r1)
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stw r27, HOST_NV_GPR(r27)(r1)
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stw r28, HOST_NV_GPR(r28)(r1)
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stw r29, HOST_NV_GPR(r29)(r1)
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stw r30, HOST_NV_GPR(r30)(r1)
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stw r31, HOST_NV_GPR(r31)(r1)
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/* Load guest non-volatiles. */
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lwz r14, VCPU_GPR(r14)(r4)
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lwz r15, VCPU_GPR(r15)(r4)
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lwz r16, VCPU_GPR(r16)(r4)
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lwz r17, VCPU_GPR(r17)(r4)
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lwz r18, VCPU_GPR(r18)(r4)
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lwz r19, VCPU_GPR(r19)(r4)
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lwz r20, VCPU_GPR(r20)(r4)
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lwz r21, VCPU_GPR(r21)(r4)
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lwz r22, VCPU_GPR(r22)(r4)
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lwz r23, VCPU_GPR(r23)(r4)
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lwz r24, VCPU_GPR(r24)(r4)
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lwz r25, VCPU_GPR(r25)(r4)
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lwz r26, VCPU_GPR(r26)(r4)
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lwz r27, VCPU_GPR(r27)(r4)
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lwz r28, VCPU_GPR(r28)(r4)
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lwz r29, VCPU_GPR(r29)(r4)
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lwz r30, VCPU_GPR(r30)(r4)
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lwz r31, VCPU_GPR(r31)(r4)
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lightweight_exit:
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stw r2, HOST_R2(r1)
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mfspr r3, SPRN_PID
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stw r3, VCPU_HOST_PID(r4)
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lwz r3, VCPU_SHADOW_PID(r4)
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mtspr SPRN_PID, r3
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#ifdef CONFIG_44x
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iccci 0, 0 /* XXX hack */
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#endif
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/* Load some guest volatiles. */
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lwz r0, VCPU_GPR(r0)(r4)
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lwz r2, VCPU_GPR(r2)(r4)
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lwz r9, VCPU_GPR(r9)(r4)
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lwz r10, VCPU_GPR(r10)(r4)
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lwz r11, VCPU_GPR(r11)(r4)
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lwz r12, VCPU_GPR(r12)(r4)
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lwz r13, VCPU_GPR(r13)(r4)
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lwz r3, VCPU_LR(r4)
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mtlr r3
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lwz r3, VCPU_XER(r4)
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mtxer r3
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/* Switch the IVPR. XXX If we take a TLB miss after this we're screwed,
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* so how do we make sure vcpu won't fault? */
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lis r8, kvmppc_booke_handlers@ha
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lwz r8, kvmppc_booke_handlers@l(r8)
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mtspr SPRN_IVPR, r8
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/* Save vcpu pointer for the exception handlers. */
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mtspr SPRN_SPRG_WVCPU, r4
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/* Can't switch the stack pointer until after IVPR is switched,
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* because host interrupt handlers would get confused. */
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lwz r1, VCPU_GPR(r1)(r4)
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/* XXX handle USPRG0 */
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/* Host interrupt handlers may have clobbered these guest-readable
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* SPRGs, so we need to reload them here with the guest's values. */
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lwz r3, VCPU_SPRG4(r4)
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mtspr SPRN_SPRG4W, r3
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lwz r3, VCPU_SPRG5(r4)
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|
mtspr SPRN_SPRG5W, r3
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|
lwz r3, VCPU_SPRG6(r4)
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|
mtspr SPRN_SPRG6W, r3
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|
lwz r3, VCPU_SPRG7(r4)
|
|
mtspr SPRN_SPRG7W, r3
|
|
|
|
#ifdef CONFIG_KVM_EXIT_TIMING
|
|
/* save enter time */
|
|
1:
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|
mfspr r6, SPRN_TBRU
|
|
mfspr r7, SPRN_TBRL
|
|
mfspr r8, SPRN_TBRU
|
|
cmpw r8, r6
|
|
bne 1b
|
|
stw r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
|
|
stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
|
|
#endif
|
|
|
|
/* Finish loading guest volatiles and jump to guest. */
|
|
lwz r3, VCPU_CTR(r4)
|
|
mtctr r3
|
|
lwz r3, VCPU_CR(r4)
|
|
mtcr r3
|
|
lwz r5, VCPU_GPR(r5)(r4)
|
|
lwz r6, VCPU_GPR(r6)(r4)
|
|
lwz r7, VCPU_GPR(r7)(r4)
|
|
lwz r8, VCPU_GPR(r8)(r4)
|
|
lwz r3, VCPU_PC(r4)
|
|
mtsrr0 r3
|
|
lwz r3, VCPU_MSR(r4)
|
|
oris r3, r3, KVMPPC_MSR_MASK@h
|
|
ori r3, r3, KVMPPC_MSR_MASK@l
|
|
mtsrr1 r3
|
|
|
|
/* Clear any debug events which occurred since we disabled MSR[DE].
|
|
* XXX This gives us a 3-instruction window in which a breakpoint
|
|
* intended for guest context could fire in the host instead. */
|
|
lis r3, 0xffff
|
|
ori r3, r3, 0xffff
|
|
mtspr SPRN_DBSR, r3
|
|
|
|
lwz r3, VCPU_GPR(r3)(r4)
|
|
lwz r4, VCPU_GPR(r4)(r4)
|
|
rfi
|