363 lines
10 KiB
C
363 lines
10 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* Momentum Computer Ocelot-C and -CS board dependent boot routines
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*
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* Copyright (C) 1996, 1997, 2001 Ralf Baechle
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* Copyright (C) 2000 RidgeRun, Inc.
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* Copyright (C) 2001 Red Hat, Inc.
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* Copyright (C) 2002 Momentum Computer
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*
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* Author: Matthew Dharm, Momentum Computer
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* mdharm@momenco.com
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*
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* Louis Hamilton, Red Hat, Inc.
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* hamilton@redhat.com [MIPS64 modifications]
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*
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* Author: RidgeRun, Inc.
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* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/bcd.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/pm.h>
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#include <linux/timex.h>
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#include <linux/vmalloc.h>
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#include <linux/mv643xx.h>
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#include <asm/time.h>
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#include <asm/bootinfo.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/marvell.h>
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#include <linux/bootmem.h>
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#include <linux/blkdev.h>
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#include "ocelot_c_fpga.h"
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unsigned long marvell_base;
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unsigned int cpu_clock;
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/* These functions are used for rebooting or halting the machine*/
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extern void momenco_ocelot_restart(char *command);
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extern void momenco_ocelot_halt(void);
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extern void momenco_ocelot_power_off(void);
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void momenco_time_init(void);
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static char reset_reason;
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void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
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static unsigned long ENTRYLO(unsigned long paddr)
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{
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return ((paddr & PAGE_MASK) |
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(_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
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_CACHE_UNCACHED)) >> 6;
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}
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/* setup code for a handoff from a version 2 PMON 2000 PROM */
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void PMON_v2_setup(void)
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{
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/* Some wired TLB entries for the MV64340 and perhiperals. The
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MV64340 is going to be hit on every IRQ anyway - there's
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absolutely no point in letting it be a random TLB entry, as
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it'll just cause needless churning of the TLB. And we use
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the other half for the serial port, which is just a PITA
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otherwise :)
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Device Physical Virtual
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MV64340 Internal Regs 0xf4000000 0xf4000000
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Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
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NVRAM (CS1) 0xfc800000 0xfc800000
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UARTs (CS2) 0xfd000000 0xfd000000
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Internal SRAM 0xfe000000 0xfe000000
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M-Systems DOC (CS3) 0xff000000 0xff000000
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*/
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printk("PMON_v2_setup\n");
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#ifdef CONFIG_64BIT
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/* marvell and extra space */
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add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
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/* fpga, rtc, and uart */
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add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
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/* m-sys and internal SRAM */
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add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
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marvell_base = 0xfffffffff4000000;
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#else
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/* marvell and extra space */
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add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
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/* fpga, rtc, and uart */
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add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
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/* m-sys and internal SRAM */
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add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
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marvell_base = 0xf4000000;
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#endif
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}
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unsigned long m48t37y_get_time(void)
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{
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#ifdef CONFIG_64BIT
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unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
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#else
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unsigned char* rtc_base = (unsigned char*)0xfc800000;
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#endif
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unsigned int year, month, day, hour, min, sec;
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unsigned long flags;
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spin_lock_irqsave(&rtc_lock, flags);
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/* stop the update */
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rtc_base[0x7ff8] = 0x40;
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year = BCD2BIN(rtc_base[0x7fff]);
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year += BCD2BIN(rtc_base[0x7ff1]) * 100;
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month = BCD2BIN(rtc_base[0x7ffe]);
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day = BCD2BIN(rtc_base[0x7ffd]);
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hour = BCD2BIN(rtc_base[0x7ffb]);
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min = BCD2BIN(rtc_base[0x7ffa]);
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sec = BCD2BIN(rtc_base[0x7ff9]);
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/* start the update */
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rtc_base[0x7ff8] = 0x00;
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spin_unlock_irqrestore(&rtc_lock, flags);
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return mktime(year, month, day, hour, min, sec);
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}
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int m48t37y_set_time(unsigned long sec)
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{
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#ifdef CONFIG_64BIT
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unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
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#else
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unsigned char* rtc_base = (unsigned char*)0xfc800000;
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#endif
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struct rtc_time tm;
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unsigned long flags;
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/* convert to a more useful format -- note months count from 0 */
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to_tm(sec, &tm);
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tm.tm_mon += 1;
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spin_lock_irqsave(&rtc_lock, flags);
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/* enable writing */
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rtc_base[0x7ff8] = 0x80;
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/* year */
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rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
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rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
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/* month */
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rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
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/* day */
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rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
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/* hour/min/sec */
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rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
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rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
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rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
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/* day of week -- not really used, but let's keep it up-to-date */
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rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
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/* disable writing */
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rtc_base[0x7ff8] = 0x00;
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spin_unlock_irqrestore(&rtc_lock, flags);
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return 0;
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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setup_irq(7, irq);
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}
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void momenco_time_init(void)
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{
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#ifdef CONFIG_CPU_SR71000
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mips_hpt_frequency = cpu_clock;
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#elif defined(CONFIG_CPU_RM7000)
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mips_hpt_frequency = cpu_clock / 2;
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#else
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#error Unknown CPU for this board
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#endif
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printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
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rtc_mips_get_time = m48t37y_get_time;
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rtc_mips_set_time = m48t37y_set_time;
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}
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void __init plat_mem_setup(void)
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{
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unsigned int tmpword;
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board_time_init = momenco_time_init;
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_machine_restart = momenco_ocelot_restart;
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_machine_halt = momenco_ocelot_halt;
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pm_power_off = momenco_ocelot_power_off;
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/*
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* initrd_start = (unsigned long)ocelot_initrd_start;
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* initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
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* initrd_below_start_ok = 1;
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*/
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/* do handoff reconfiguration */
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PMON_v2_setup();
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/* shut down ethernet ports, just to be sure our memory doesn't get
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* corrupted by random ethernet traffic.
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*/
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MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
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MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
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MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
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MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
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do {}
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while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
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do {}
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while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
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do {}
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while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
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do {}
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while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
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MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
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MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
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MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
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MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
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/* Turn off the Bit-Error LED */
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OCELOT_FPGA_WRITE(0x80, CLR);
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tmpword = OCELOT_FPGA_READ(BOARDREV);
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#ifdef CONFIG_CPU_SR71000
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if (tmpword < 26)
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printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
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'A'+tmpword);
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else
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printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
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tmpword);
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#else
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if (tmpword < 26)
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printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
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'A'+tmpword);
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else
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printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
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tmpword);
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#endif
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tmpword = OCELOT_FPGA_READ(FPGA_REV);
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printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
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tmpword = OCELOT_FPGA_READ(RESET_STATUS);
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printk("Reset reason: 0x%x\n", tmpword);
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switch (tmpword) {
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case 0x1:
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printk(" - Power-up reset\n");
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break;
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case 0x2:
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printk(" - Push-button reset\n");
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break;
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case 0x4:
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printk(" - cPCI bus reset\n");
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break;
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case 0x8:
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printk(" - Watchdog reset\n");
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break;
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case 0x10:
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printk(" - Software reset\n");
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break;
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default:
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printk(" - Unknown reset cause\n");
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}
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reset_reason = tmpword;
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OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
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tmpword = OCELOT_FPGA_READ(CPCI_ID);
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printk("cPCI ID register: 0x%02x\n", tmpword);
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printk(" - Slot number: %d\n", tmpword & 0x1f);
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printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
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printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
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tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
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printk("Board Status register: 0x%02x\n", tmpword);
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printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
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printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
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printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
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printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
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switch(tmpword &3) {
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case 3:
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/* 512MiB */
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add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
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break;
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case 2:
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/* 256MiB */
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add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
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break;
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case 1:
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/* 128MiB */
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add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
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break;
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case 0:
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/* 1GiB -- needs CONFIG_HIGHMEM */
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add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
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break;
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}
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}
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/*
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* This needs to be one of the first initcalls, because no I/O port access
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* can work before this
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*/
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static int io_base_ioremap(void)
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{
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void __iomem * io_remap_range = ioremap(0xc0000000UL, 0x10000);
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if (!io_remap_range)
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panic("Could not ioremap I/O port range");
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set_io_port_base((unsigned long) io_remap_range);
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return 0;
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}
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module_init(io_base_ioremap);
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