3efc333e7f
The spinlock_types.h merge renamed the structure for raw_spinlock_t to match ppc64. In doing so some of the spinlock macros/functions needed to be updated to match. Apparently, this seems to only be caught when building power3. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
165 lines
3.1 KiB
C
165 lines
3.1 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/system.h>
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/*
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* Simple spin lock operations.
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*
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* (the type definitions are in asm/raw_spinlock_types.h)
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*/
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#define __raw_spin_is_locked(x) ((x)->slock != 0)
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"b 1f # __raw_spin_lock\n\
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2: lwzx %0,0,%1\n\
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cmpwi 0,%0,0\n\
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bne+ 2b\n\
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1: lwarx %0,0,%1\n\
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cmpwi 0,%0,0\n\
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bne- 2b\n"
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PPC405_ERR77(0,%1)
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" stwcx. %2,0,%1\n\
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bne- 2b\n\
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isync"
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: "=&r"(tmp)
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: "r"(&lock->slock), "r"(1)
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: "cr0", "memory");
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__("eieio # __raw_spin_unlock": : :"memory");
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lock->slock = 0;
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}
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#define __raw_spin_trylock(l) (!test_and_set_bit(0,(volatile unsigned long *)(&(l)->slock)))
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
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#define __raw_write_can_lock(rw) (!(rw)->lock)
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static __inline__ int __raw_read_trylock(raw_rwlock_t *rw)
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{
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signed int tmp;
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__asm__ __volatile__(
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"2: lwarx %0,0,%1 # read_trylock\n\
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addic. %0,%0,1\n\
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ble- 1f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 2b\n\
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isync\n\
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1:"
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: "=&r"(tmp)
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: "r"(&rw->lock)
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: "cr0", "memory");
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return tmp > 0;
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}
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static __inline__ void __raw_read_lock(raw_rwlock_t *rw)
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{
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signed int tmp;
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__asm__ __volatile__(
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"b 2f # read_lock\n\
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1: lwzx %0,0,%1\n\
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cmpwi 0,%0,0\n\
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blt+ 1b\n\
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2: lwarx %0,0,%1\n\
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addic. %0,%0,1\n\
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ble- 1b\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 2b\n\
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isync"
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: "=&r"(tmp)
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: "r"(&rw->lock)
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: "cr0", "memory");
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}
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static __inline__ void __raw_read_unlock(raw_rwlock_t *rw)
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{
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signed int tmp;
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__asm__ __volatile__(
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"eieio # read_unlock\n\
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1: lwarx %0,0,%1\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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: "=&r"(tmp)
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: "r"(&rw->lock)
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: "cr0", "memory");
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}
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static __inline__ int __raw_write_trylock(raw_rwlock_t *rw)
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{
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signed int tmp;
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__asm__ __volatile__(
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"2: lwarx %0,0,%1 # write_trylock\n\
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cmpwi 0,%0,0\n\
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bne- 1f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %2,0,%1\n\
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bne- 2b\n\
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isync\n\
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1:"
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: "=&r"(tmp)
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: "r"(&rw->lock), "r"(-1)
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: "cr0", "memory");
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return tmp == 0;
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}
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static __inline__ void __raw_write_lock(raw_rwlock_t *rw)
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{
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signed int tmp;
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__asm__ __volatile__(
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"b 2f # write_lock\n\
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1: lwzx %0,0,%1\n\
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cmpwi 0,%0,0\n\
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bne+ 1b\n\
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2: lwarx %0,0,%1\n\
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cmpwi 0,%0,0\n\
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bne- 1b\n"
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PPC405_ERR77(0,%1)
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" stwcx. %2,0,%1\n\
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bne- 2b\n\
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isync"
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: "=&r"(tmp)
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: "r"(&rw->lock), "r"(-1)
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: "cr0", "memory");
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}
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static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
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{
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__asm__ __volatile__("eieio # write_unlock": : :"memory");
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rw->lock = 0;
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}
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#endif /* __ASM_SPINLOCK_H */
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