34bf6bae32
The new AMD/HYGON topology parser evaluates the SMT information in CPUID leaf
0x8000001e unconditionally while the original code restricted it to CPUs with
family 0x17 and greater.
This breaks family 0x15 CPUs which advertise that leaf and have a non-zero
value in the SMT section. The machine boots, but the scheduler complains loudly
about the mismatch of the core IDs:
WARNING: CPU: 1 PID: 0 at kernel/sched/core.c:6482 sched_cpu_starting+0x183/0x250
WARNING: CPU: 0 PID: 1 at kernel/sched/topology.c:2408 build_sched_domains+0x76b/0x12b0
Add the condition back to cure it.
[ bp: Make it actually build because grandpa is not concerned with
trivial stuff. :-P ]
Fixes: f7fb3b2dd9
("x86/cpu: Provide an AMD/HYGON specific topology parser")
Closes: https://gitlab.archlinux.org/archlinux/packaging/packages/linux/-/issues/56
Reported-by: Tim Teichmann <teichmanntim@outlook.de>
Reported-by: Christian Heusel <christian@heusel.eu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Tested-by: Tim Teichmann <teichmanntim@outlook.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/7skhx6mwe4hxiul64v6azhlxnokheorksqsdbp7qw6g2jduf6c@7b5pvomauugk
218 lines
6.0 KiB
C
218 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/cpu.h>
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#include <asm/apic.h>
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#include <asm/memtype.h>
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#include <asm/processor.h>
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#include "cpu.h"
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static bool parse_8000_0008(struct topo_scan *tscan)
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{
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struct {
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// ecx
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u32 cpu_nthreads : 8, // Number of physical threads - 1
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: 4, // Reserved
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apicid_coreid_len : 4, // Number of thread core ID bits (shift) in APIC ID
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perf_tsc_len : 2, // Performance time-stamp counter size
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: 14; // Reserved
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} ecx;
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unsigned int sft;
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if (tscan->c->extended_cpuid_level < 0x80000008)
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return false;
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cpuid_leaf_reg(0x80000008, CPUID_ECX, &ecx);
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/* If the thread bits are 0, then get the shift value from ecx.cpu_nthreads */
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sft = ecx.apicid_coreid_len;
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if (!sft)
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sft = get_count_order(ecx.cpu_nthreads + 1);
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/*
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* cpu_nthreads describes the number of threads in the package
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* sft is the number of APIC ID bits per package
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*
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* As the number of actual threads per core is not described in
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* this leaf, just set the CORE domain shift and let the later
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* parsers set SMT shift. Assume one thread per core by default
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* which is correct if there are no other CPUID leafs to parse.
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*/
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topology_update_dom(tscan, TOPO_SMT_DOMAIN, 0, 1);
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topology_set_dom(tscan, TOPO_CORE_DOMAIN, sft, ecx.cpu_nthreads + 1);
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return true;
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}
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static void store_node(struct topo_scan *tscan, u16 nr_nodes, u16 node_id)
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{
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/*
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* Starting with Fam 17h the DIE domain could probably be used to
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* retrieve the node info on AMD/HYGON. Analysis of CPUID dumps
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* suggests it's the topmost bit(s) of the CPU cores area, but
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* that's guess work and neither enumerated nor documented.
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*
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* Up to Fam 16h this does not work at all and the legacy node ID
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* has to be used.
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*/
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tscan->amd_nodes_per_pkg = nr_nodes;
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tscan->amd_node_id = node_id;
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}
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static bool parse_8000_001e(struct topo_scan *tscan, bool has_topoext)
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{
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struct {
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// eax
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u32 ext_apic_id : 32; // Extended APIC ID
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// ebx
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u32 core_id : 8, // Unique per-socket logical core unit ID
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core_nthreads : 8, // #Threads per core (zero-based)
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: 16; // Reserved
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// ecx
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u32 node_id : 8, // Node (die) ID of invoking logical CPU
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nnodes_per_socket : 3, // #nodes in invoking logical CPU's package/socket
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: 21; // Reserved
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// edx
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u32 : 32; // Reserved
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} leaf;
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if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
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return false;
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cpuid_leaf(0x8000001e, &leaf);
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tscan->c->topo.initial_apicid = leaf.ext_apic_id;
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/*
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* If leaf 0xb is available, then the domain shifts are set
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* already and nothing to do here. Only valid for family >= 0x17.
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*/
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if (!has_topoext && tscan->c->x86 >= 0x17) {
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/*
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* Leaf 0x80000008 set the CORE domain shift already.
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* Update the SMT domain, but do not propagate it.
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*/
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unsigned int nthreads = leaf.core_nthreads + 1;
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topology_update_dom(tscan, TOPO_SMT_DOMAIN, get_count_order(nthreads), nthreads);
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}
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store_node(tscan, leaf.nnodes_per_socket + 1, leaf.node_id);
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if (tscan->c->x86_vendor == X86_VENDOR_AMD) {
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if (tscan->c->x86 == 0x15)
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tscan->c->topo.cu_id = leaf.core_id;
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cacheinfo_amd_init_llc_id(tscan->c, leaf.node_id);
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} else {
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/*
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* Package ID is ApicId[6..] on certain Hygon CPUs. See
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* commit e0ceeae708ce for explanation. The topology info
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* is screwed up: The package shift is always 6 and the
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* node ID is bit [4:5].
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*/
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if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) && tscan->c->x86_model <= 0x3) {
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topology_set_dom(tscan, TOPO_CORE_DOMAIN, 6,
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tscan->dom_ncpus[TOPO_CORE_DOMAIN]);
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}
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cacheinfo_hygon_init_llc_id(tscan->c);
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}
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return true;
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}
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static void parse_fam10h_node_id(struct topo_scan *tscan)
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{
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union {
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struct {
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u64 node_id : 3,
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nodes_per_pkg : 3,
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unused : 58;
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};
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u64 msr;
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} nid;
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if (!boot_cpu_has(X86_FEATURE_NODEID_MSR))
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return;
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rdmsrl(MSR_FAM10H_NODE_ID, nid.msr);
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store_node(tscan, nid.nodes_per_pkg + 1, nid.node_id);
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tscan->c->topo.llc_id = nid.node_id;
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}
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static void legacy_set_llc(struct topo_scan *tscan)
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{
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unsigned int apicid = tscan->c->topo.initial_apicid;
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/* If none of the parsers set LLC ID then use the die ID for it. */
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if (tscan->c->topo.llc_id == BAD_APICID)
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tscan->c->topo.llc_id = apicid >> tscan->dom_shifts[TOPO_CORE_DOMAIN];
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}
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static void topoext_fixup(struct topo_scan *tscan)
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{
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struct cpuinfo_x86 *c = tscan->c;
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u64 msrval;
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/* Try to re-enable TopologyExtensions if switched off by BIOS */
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if (cpu_has(c, X86_FEATURE_TOPOEXT) || c->x86_vendor != X86_VENDOR_AMD ||
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c->x86 != 0x15 || c->x86_model < 0x10 || c->x86_model > 0x6f)
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return;
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if (msr_set_bit(0xc0011005, 54) <= 0)
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return;
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rdmsrl(0xc0011005, msrval);
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if (msrval & BIT_64(54)) {
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set_cpu_cap(c, X86_FEATURE_TOPOEXT);
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pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
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}
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}
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static void parse_topology_amd(struct topo_scan *tscan)
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{
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bool has_topoext = false;
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/*
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* If the extended topology leaf 0x8000_001e is available
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* try to get SMT, CORE, TILE, and DIE shifts from extended
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* CPUID leaf 0x8000_0026 on supported processors first. If
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* extended CPUID leaf 0x8000_0026 is not supported, try to
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* get SMT and CORE shift from leaf 0xb first, then try to
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* get the CORE shift from leaf 0x8000_0008.
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*/
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if (cpu_feature_enabled(X86_FEATURE_TOPOEXT))
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has_topoext = cpu_parse_topology_ext(tscan);
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if (!has_topoext && !parse_8000_0008(tscan))
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return;
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/* Prefer leaf 0x8000001e if available */
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if (parse_8000_001e(tscan, has_topoext))
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return;
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/* Try the NODEID MSR */
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parse_fam10h_node_id(tscan);
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}
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void cpu_parse_topology_amd(struct topo_scan *tscan)
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{
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tscan->amd_nodes_per_pkg = 1;
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topoext_fixup(tscan);
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parse_topology_amd(tscan);
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legacy_set_llc(tscan);
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if (tscan->amd_nodes_per_pkg > 1)
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set_cpu_cap(tscan->c, X86_FEATURE_AMD_DCM);
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}
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void cpu_topology_fixup_amd(struct topo_scan *tscan)
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{
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struct cpuinfo_x86 *c = tscan->c;
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/*
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* Adjust the core_id relative to the node when there is more than
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* one node.
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*/
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if (tscan->c->x86 < 0x17 && tscan->amd_nodes_per_pkg > 1)
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c->topo.core_id %= tscan->dom_ncpus[TOPO_CORE_DOMAIN] / tscan->amd_nodes_per_pkg;
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}
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