f9bbb8ad0c
Generally, MCA information for an error is gathered on the CPU that reported the error. In this case, CPU-specific information from the running CPU will be correct. However, this will be incorrect if the MCA information is gathered while running on a CPU that didn't report the error. One example is creating an MCA record using mce_prep_record() for errors reported from ACPI. Split mce_prep_record() so that there is a helper function to gather common, i.e. not CPU-specific, information and another helper for CPU-specific information. Leave mce_prep_record() defined as-is for the common case when running on the reporting CPU. Get MCG_CAP in the global helper even though the register is per-CPU. This value is not already cached per-CPU like other values. And it does not assist with any per-CPU decoding or handling. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Nikolay Borisov <nik.borisov@suse.com> Link: https://lore.kernel.org/r/20240730182958.4117158-3-yazen.ghannam@amd.com Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
340 lines
8.9 KiB
C
340 lines
8.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __X86_MCE_INTERNAL_H__
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#define __X86_MCE_INTERNAL_H__
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#undef pr_fmt
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#define pr_fmt(fmt) "mce: " fmt
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#include <linux/device.h>
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#include <asm/mce.h>
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enum severity_level {
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MCE_NO_SEVERITY,
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MCE_DEFERRED_SEVERITY,
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MCE_UCNA_SEVERITY = MCE_DEFERRED_SEVERITY,
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MCE_KEEP_SEVERITY,
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MCE_SOME_SEVERITY,
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MCE_AO_SEVERITY,
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MCE_UC_SEVERITY,
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MCE_AR_SEVERITY,
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MCE_PANIC_SEVERITY,
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};
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extern struct blocking_notifier_head x86_mce_decoder_chain;
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#define INITIAL_CHECK_INTERVAL 5 * 60 /* 5 minutes */
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struct mce_evt_llist {
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struct llist_node llnode;
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struct mce mce;
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};
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void mce_gen_pool_process(struct work_struct *__unused);
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bool mce_gen_pool_empty(void);
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int mce_gen_pool_add(struct mce *mce);
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int mce_gen_pool_init(void);
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struct llist_node *mce_gen_pool_prepare_records(void);
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int mce_severity(struct mce *a, struct pt_regs *regs, char **msg, bool is_excp);
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struct dentry *mce_get_debugfs_dir(void);
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extern mce_banks_t mce_banks_ce_disabled;
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#ifdef CONFIG_X86_MCE_INTEL
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void mce_intel_handle_storm(int bank, bool on);
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void cmci_disable_bank(int bank);
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void intel_init_cmci(void);
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void intel_init_lmce(void);
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void intel_clear_lmce(void);
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bool intel_filter_mce(struct mce *m);
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bool intel_mce_usable_address(struct mce *m);
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#else
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static inline void mce_intel_handle_storm(int bank, bool on) { }
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static inline void cmci_disable_bank(int bank) { }
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static inline void intel_init_cmci(void) { }
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static inline void intel_init_lmce(void) { }
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static inline void intel_clear_lmce(void) { }
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static inline bool intel_filter_mce(struct mce *m) { return false; }
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static inline bool intel_mce_usable_address(struct mce *m) { return false; }
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#endif
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void mce_timer_kick(bool storm);
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#ifdef CONFIG_X86_MCE_THRESHOLD
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void cmci_storm_begin(unsigned int bank);
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void cmci_storm_end(unsigned int bank);
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void mce_track_storm(struct mce *mce);
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void mce_inherit_storm(unsigned int bank);
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bool mce_get_storm_mode(void);
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void mce_set_storm_mode(bool storm);
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#else
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static inline void cmci_storm_begin(unsigned int bank) {}
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static inline void cmci_storm_end(unsigned int bank) {}
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static inline void mce_track_storm(struct mce *mce) {}
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static inline void mce_inherit_storm(unsigned int bank) {}
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static inline bool mce_get_storm_mode(void) { return false; }
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static inline void mce_set_storm_mode(bool storm) {}
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#endif
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/*
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* history: Bitmask tracking errors occurrence. Each set bit
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* represents an error seen.
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*
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* timestamp: Last time (in jiffies) that the bank was polled.
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* in_storm_mode: Is this bank in storm mode?
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* poll_only: Bank does not support CMCI, skip storm tracking.
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*/
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struct storm_bank {
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u64 history;
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u64 timestamp;
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bool in_storm_mode;
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bool poll_only;
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};
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#define NUM_HISTORY_BITS (sizeof(u64) * BITS_PER_BYTE)
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/* How many errors within the history buffer mark the start of a storm. */
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#define STORM_BEGIN_THRESHOLD 5
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/*
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* How many polls of machine check bank without an error before declaring
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* the storm is over. Since it is tracked by the bitmasks in the history
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* field of struct storm_bank the mask is 30 bits [0 ... 29].
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*/
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#define STORM_END_POLL_THRESHOLD 29
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/*
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* banks: per-cpu, per-bank details
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* stormy_bank_count: count of MC banks in storm state
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* poll_mode: CPU is in poll mode
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*/
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struct mca_storm_desc {
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struct storm_bank banks[MAX_NR_BANKS];
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u8 stormy_bank_count;
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bool poll_mode;
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};
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DECLARE_PER_CPU(struct mca_storm_desc, storm_desc);
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#ifdef CONFIG_ACPI_APEI
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int apei_write_mce(struct mce *m);
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ssize_t apei_read_mce(struct mce *m, u64 *record_id);
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int apei_check_mce(void);
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int apei_clear_mce(u64 record_id);
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#else
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static inline int apei_write_mce(struct mce *m)
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{
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return -EINVAL;
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}
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static inline ssize_t apei_read_mce(struct mce *m, u64 *record_id)
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{
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return 0;
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}
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static inline int apei_check_mce(void)
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{
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return 0;
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}
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static inline int apei_clear_mce(u64 record_id)
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{
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return -EINVAL;
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}
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#endif
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/*
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* We consider records to be equivalent if bank+status+addr+misc all match.
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* This is only used when the system is going down because of a fatal error
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* to avoid cluttering the console log with essentially repeated information.
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* In normal processing all errors seen are logged.
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*/
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static inline bool mce_cmp(struct mce *m1, struct mce *m2)
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{
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return m1->bank != m2->bank ||
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m1->status != m2->status ||
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m1->addr != m2->addr ||
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m1->misc != m2->misc;
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}
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extern struct device_attribute dev_attr_trigger;
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#ifdef CONFIG_X86_MCELOG_LEGACY
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void mce_work_trigger(void);
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void mce_register_injector_chain(struct notifier_block *nb);
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void mce_unregister_injector_chain(struct notifier_block *nb);
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#else
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static inline void mce_work_trigger(void) { }
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static inline void mce_register_injector_chain(struct notifier_block *nb) { }
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static inline void mce_unregister_injector_chain(struct notifier_block *nb) { }
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#endif
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struct mca_config {
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__u64 lmce_disabled : 1,
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disabled : 1,
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ser : 1,
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recovery : 1,
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bios_cmci_threshold : 1,
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/* Proper #MC exception handler is set */
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initialized : 1,
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__reserved : 58;
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bool dont_log_ce;
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bool cmci_disabled;
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bool ignore_ce;
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bool print_all;
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int monarch_timeout;
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int panic_timeout;
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u32 rip_msr;
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s8 bootlog;
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};
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extern struct mca_config mca_cfg;
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DECLARE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
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struct mce_vendor_flags {
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/*
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* Indicates that overflow conditions are not fatal, when set.
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*/
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__u64 overflow_recov : 1,
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/*
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* (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
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* Recovery. It indicates support for data poisoning in HW and deferred
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* error interrupts.
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*/
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succor : 1,
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/*
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* (AMD) SMCA: This bit indicates support for Scalable MCA which expands
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* the register space for each MCA bank and also increases number of
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* banks. Also, to accommodate the new banks and registers, the MCA
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* register space is moved to a new MSR range.
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*/
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smca : 1,
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/* Zen IFU quirk */
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zen_ifu_quirk : 1,
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/* AMD-style error thresholding banks present. */
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amd_threshold : 1,
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/* Pentium, family 5-style MCA */
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p5 : 1,
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/* Centaur Winchip C6-style MCA */
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winchip : 1,
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/* SandyBridge IFU quirk */
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snb_ifu_quirk : 1,
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/* Skylake, Cascade Lake, Cooper Lake REP;MOVS* quirk */
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skx_repmov_quirk : 1,
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__reserved_0 : 55;
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};
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extern struct mce_vendor_flags mce_flags;
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struct mce_bank {
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/* subevents to enable */
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u64 ctl;
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/* initialise bank? */
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__u64 init : 1,
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/*
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* (AMD) MCA_CONFIG[McaLsbInStatusSupported]: When set, this bit indicates
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* the LSB field is found in MCA_STATUS and not in MCA_ADDR.
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*/
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lsb_in_status : 1,
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__reserved_1 : 62;
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};
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DECLARE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
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enum mca_msr {
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MCA_CTL,
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MCA_STATUS,
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MCA_ADDR,
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MCA_MISC,
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};
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/* Decide whether to add MCE record to MCE event pool or filter it out. */
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extern bool filter_mce(struct mce *m);
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void mce_prep_record_common(struct mce *m);
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void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m);
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#ifdef CONFIG_X86_MCE_AMD
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extern bool amd_filter_mce(struct mce *m);
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bool amd_mce_usable_address(struct mce *m);
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/*
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* If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits
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* [56:0] of MCA_STATUS, else in bits [55:0] of MCA_ADDR.
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*/
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static __always_inline void smca_extract_err_addr(struct mce *m)
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{
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u8 lsb;
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if (!mce_flags.smca)
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return;
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if (this_cpu_ptr(mce_banks_array)[m->bank].lsb_in_status) {
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lsb = (m->status >> 24) & 0x3f;
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m->addr &= GENMASK_ULL(56, lsb);
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return;
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}
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lsb = (m->addr >> 56) & 0x3f;
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m->addr &= GENMASK_ULL(55, lsb);
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}
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#else
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static inline bool amd_filter_mce(struct mce *m) { return false; }
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static inline bool amd_mce_usable_address(struct mce *m) { return false; }
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static inline void smca_extract_err_addr(struct mce *m) { }
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#endif
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#ifdef CONFIG_X86_ANCIENT_MCE
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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noinstr void pentium_machine_check(struct pt_regs *regs);
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noinstr void winchip_machine_check(struct pt_regs *regs);
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static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
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#else
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static __always_inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
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static __always_inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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static __always_inline void enable_p5_mce(void) {}
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static __always_inline void pentium_machine_check(struct pt_regs *regs) {}
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static __always_inline void winchip_machine_check(struct pt_regs *regs) {}
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#endif
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noinstr u64 mce_rdmsrl(u32 msr);
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static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)
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{
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if (cpu_feature_enabled(X86_FEATURE_SMCA)) {
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switch (reg) {
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case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank);
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case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank);
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case MCA_MISC: return MSR_AMD64_SMCA_MCx_MISC(bank);
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case MCA_STATUS: return MSR_AMD64_SMCA_MCx_STATUS(bank);
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}
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}
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switch (reg) {
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case MCA_CTL: return MSR_IA32_MCx_CTL(bank);
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case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank);
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case MCA_MISC: return MSR_IA32_MCx_MISC(bank);
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case MCA_STATUS: return MSR_IA32_MCx_STATUS(bank);
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}
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return 0;
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}
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extern void (*mc_poll_banks)(void);
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#endif /* __X86_MCE_INTERNAL_H__ */
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