c062bcab59
Add RPMh Network-On-Chip Interconnect support for the SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231123-topic-sm8650-upstream-interconnect-v2-2-7e050874f59b@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
144 lines
4.9 KiB
C
144 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* SM8650 interconnect IDs
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*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H
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#define __DRIVERS_INTERCONNECT_QCOM_SM8650_H
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#define SM8650_MASTER_A1NOC_SNOC 0
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#define SM8650_MASTER_A2NOC_SNOC 1
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#define SM8650_MASTER_ANOC_PCIE_GEM_NOC 2
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#define SM8650_MASTER_APPSS_PROC 3
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#define SM8650_MASTER_CAMNOC_HF 4
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#define SM8650_MASTER_CAMNOC_ICP 5
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#define SM8650_MASTER_CAMNOC_SF 6
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#define SM8650_MASTER_CDSP_HCP 7
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#define SM8650_MASTER_CDSP_PROC 8
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#define SM8650_MASTER_CNOC_CFG 9
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#define SM8650_MASTER_CNOC_MNOC_CFG 10
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#define SM8650_MASTER_COMPUTE_NOC 11
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#define SM8650_MASTER_CRYPTO 12
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#define SM8650_MASTER_GEM_NOC_CNOC 13
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#define SM8650_MASTER_GEM_NOC_PCIE_SNOC 14
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#define SM8650_MASTER_GFX3D 15
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#define SM8650_MASTER_GIC 16
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#define SM8650_MASTER_GPU_TCU 17
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#define SM8650_MASTER_IPA 18
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#define SM8650_MASTER_LLCC 19
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#define SM8650_MASTER_LPASS_GEM_NOC 20
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#define SM8650_MASTER_LPASS_LPINOC 21
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#define SM8650_MASTER_LPASS_PROC 22
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#define SM8650_MASTER_LPIAON_NOC 23
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#define SM8650_MASTER_MDP 24
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#define SM8650_MASTER_MNOC_HF_MEM_NOC 25
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#define SM8650_MASTER_MNOC_SF_MEM_NOC 26
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#define SM8650_MASTER_MSS_PROC 27
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#define SM8650_MASTER_PCIE_0 28
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#define SM8650_MASTER_PCIE_1 29
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#define SM8650_MASTER_PCIE_ANOC_CFG 30
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#define SM8650_MASTER_QDSS_BAM 31
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#define SM8650_MASTER_QDSS_ETR 32
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#define SM8650_MASTER_QDSS_ETR_1 33
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#define SM8650_MASTER_QSPI_0 34
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#define SM8650_MASTER_QUP_1 35
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#define SM8650_MASTER_QUP_2 36
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#define SM8650_MASTER_QUP_3 37
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#define SM8650_MASTER_QUP_CORE_0 38
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#define SM8650_MASTER_QUP_CORE_1 39
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#define SM8650_MASTER_QUP_CORE_2 40
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#define SM8650_MASTER_SDCC_2 41
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#define SM8650_MASTER_SDCC_4 42
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#define SM8650_MASTER_SNOC_SF_MEM_NOC 43
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#define SM8650_MASTER_SP 44
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#define SM8650_MASTER_SYS_TCU 45
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#define SM8650_MASTER_UBWC_P 46
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#define SM8650_MASTER_UBWC_P_TCU 47
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#define SM8650_MASTER_UFS_MEM 48
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#define SM8650_MASTER_USB3_0 49
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#define SM8650_MASTER_VIDEO 50
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#define SM8650_MASTER_VIDEO_CV_PROC 51
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#define SM8650_MASTER_VIDEO_PROC 52
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#define SM8650_MASTER_VIDEO_V_PROC 53
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#define SM8650_SLAVE_A1NOC_SNOC 54
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#define SM8650_SLAVE_A2NOC_SNOC 55
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#define SM8650_SLAVE_AHB2PHY_NORTH 56
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#define SM8650_SLAVE_AHB2PHY_SOUTH 57
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#define SM8650_SLAVE_ANOC_PCIE_GEM_NOC 58
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#define SM8650_SLAVE_AOSS 59
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#define SM8650_SLAVE_APPSS 60
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#define SM8650_SLAVE_CAMERA_CFG 61
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#define SM8650_SLAVE_CDSP_MEM_NOC 62
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#define SM8650_SLAVE_CLK_CTL 63
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#define SM8650_SLAVE_CNOC_CFG 64
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#define SM8650_SLAVE_CNOC_MNOC_CFG 65
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#define SM8650_SLAVE_CNOC_MSS 66
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#define SM8650_SLAVE_CPR_HMX 67
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#define SM8650_SLAVE_CPR_NSPCX 68
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#define SM8650_SLAVE_CRYPTO_0_CFG 69
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#define SM8650_SLAVE_CX_RDPM 70
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#define SM8650_SLAVE_DDRSS_CFG 71
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#define SM8650_SLAVE_DISPLAY_CFG 72
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#define SM8650_SLAVE_EBI1 73
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#define SM8650_SLAVE_GEM_NOC_CNOC 74
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#define SM8650_SLAVE_GFX3D_CFG 75
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#define SM8650_SLAVE_I2C 76
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#define SM8650_SLAVE_I3C_IBI0_CFG 77
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#define SM8650_SLAVE_I3C_IBI1_CFG 78
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#define SM8650_SLAVE_IMEM 79
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#define SM8650_SLAVE_IMEM_CFG 80
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#define SM8650_SLAVE_IPA_CFG 81
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#define SM8650_SLAVE_IPC_ROUTER_CFG 82
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#define SM8650_SLAVE_LLCC 83
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#define SM8650_SLAVE_LPASS_GEM_NOC 84
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#define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC 85
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#define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC 86
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#define SM8650_SLAVE_MEM_NOC_PCIE_SNOC 87
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#define SM8650_SLAVE_MNOC_HF_MEM_NOC 88
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#define SM8650_SLAVE_MNOC_SF_MEM_NOC 89
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#define SM8650_SLAVE_MX_2_RDPM 90
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#define SM8650_SLAVE_MX_RDPM 91
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#define SM8650_SLAVE_NSP_QTB_CFG 92
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#define SM8650_SLAVE_PCIE_0 93
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#define SM8650_SLAVE_PCIE_1 94
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#define SM8650_SLAVE_PCIE_0_CFG 95
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#define SM8650_SLAVE_PCIE_1_CFG 96
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#define SM8650_SLAVE_PCIE_ANOC_CFG 97
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#define SM8650_SLAVE_PCIE_RSCC 98
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#define SM8650_SLAVE_PDM 99
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#define SM8650_SLAVE_PRNG 100
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#define SM8650_SLAVE_QDSS_CFG 101
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#define SM8650_SLAVE_QDSS_STM 102
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#define SM8650_SLAVE_QSPI_0 103
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#define SM8650_SLAVE_QUP_1 104
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#define SM8650_SLAVE_QUP_2 105
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#define SM8650_SLAVE_QUP_3 106
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#define SM8650_SLAVE_QUP_CORE_0 107
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#define SM8650_SLAVE_QUP_CORE_1 108
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#define SM8650_SLAVE_QUP_CORE_2 109
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#define SM8650_SLAVE_RBCPR_CX_CFG 110
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#define SM8650_SLAVE_RBCPR_MMCX_CFG 111
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#define SM8650_SLAVE_RBCPR_MXA_CFG 112
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#define SM8650_SLAVE_RBCPR_MXC_CFG 113
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#define SM8650_SLAVE_SDCC_2 114
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#define SM8650_SLAVE_SDCC_4 115
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#define SM8650_SLAVE_SERVICE_CNOC 116
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#define SM8650_SLAVE_SERVICE_CNOC_CFG 117
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#define SM8650_SLAVE_SERVICE_MNOC 118
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#define SM8650_SLAVE_SERVICE_PCIE_ANOC 119
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#define SM8650_SLAVE_SNOC_GEM_NOC_SF 120
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#define SM8650_SLAVE_SPSS_CFG 121
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#define SM8650_SLAVE_TCSR 122
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#define SM8650_SLAVE_TCU 123
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#define SM8650_SLAVE_TLMM 124
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#define SM8650_SLAVE_TME_CFG 125
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#define SM8650_SLAVE_UFS_MEM_CFG 126
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#define SM8650_SLAVE_USB3_0 127
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#define SM8650_SLAVE_VENUS_CFG 128
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#define SM8650_SLAVE_VSENSE_CTRL_CFG 129
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#endif
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