4a1574cea0
Add a driver that handles the different NoCs found on SM7150, based on the downstream dtb. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240222174250.80493-3-danila@jiaxyga.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
141 lines
4.9 KiB
C
141 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Qualcomm #define SM7150 interconnect IDs
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*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SM7150_H
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#define __DRIVERS_INTERCONNECT_QCOM_SM7150_H
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#define SM7150_A1NOC_SNOC_MAS 0
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#define SM7150_A1NOC_SNOC_SLV 1
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#define SM7150_A2NOC_SNOC_MAS 2
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#define SM7150_A2NOC_SNOC_SLV 3
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#define SM7150_MASTER_A1NOC_CFG 4
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#define SM7150_MASTER_A2NOC_CFG 5
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#define SM7150_MASTER_AMPSS_M0 6
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#define SM7150_MASTER_CAMNOC_HF0 7
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#define SM7150_MASTER_CAMNOC_HF0_UNCOMP 8
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#define SM7150_MASTER_CAMNOC_NRT 9
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#define SM7150_MASTER_CAMNOC_NRT_UNCOMP 10
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#define SM7150_MASTER_CAMNOC_RT 11
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#define SM7150_MASTER_CAMNOC_RT_UNCOMP 12
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#define SM7150_MASTER_CAMNOC_SF 13
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#define SM7150_MASTER_CAMNOC_SF_UNCOMP 14
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#define SM7150_MASTER_CNOC_A2NOC 15
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#define SM7150_MASTER_CNOC_DC_NOC 16
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#define SM7150_MASTER_CNOC_MNOC_CFG 17
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#define SM7150_MASTER_COMPUTE_NOC 18
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#define SM7150_MASTER_CRYPTO_CORE_0 19
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#define SM7150_MASTER_EMMC 20
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#define SM7150_MASTER_GEM_NOC_CFG 21
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#define SM7150_MASTER_GEM_NOC_PCIE_SNOC 22
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#define SM7150_MASTER_GEM_NOC_SNOC 23
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#define SM7150_MASTER_GIC 24
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#define SM7150_MASTER_GRAPHICS_3D 25
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#define SM7150_MASTER_IPA 26
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#define SM7150_MASTER_LLCC 27
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#define SM7150_MASTER_MDP_PORT0 28
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#define SM7150_MASTER_MDP_PORT1 29
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#define SM7150_MASTER_MNOC_HF_MEM_NOC 30
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#define SM7150_MASTER_MNOC_SF_MEM_NOC 31
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#define SM7150_MASTER_NPU 32
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#define SM7150_MASTER_PCIE 33
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#define SM7150_MASTER_PIMEM 34
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#define SM7150_MASTER_QDSS_BAM 35
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#define SM7150_MASTER_QDSS_DAP 36
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#define SM7150_MASTER_QDSS_ETR 37
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#define SM7150_MASTER_QUP_0 38
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#define SM7150_MASTER_QUP_1 39
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#define SM7150_MASTER_ROTATOR 40
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#define SM7150_MASTER_SDCC_2 41
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#define SM7150_MASTER_SDCC_4 42
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#define SM7150_MASTER_SNOC_CFG 43
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#define SM7150_MASTER_SNOC_GC_MEM_NOC 44
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#define SM7150_MASTER_SNOC_SF_MEM_NOC 45
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#define SM7150_MASTER_SPDM 46
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#define SM7150_MASTER_SYS_TCU 47
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#define SM7150_MASTER_TSIF 48
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#define SM7150_MASTER_UFS_MEM 49
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#define SM7150_MASTER_USB3 50
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#define SM7150_MASTER_VIDEO_P0 51
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#define SM7150_MASTER_VIDEO_P1 52
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#define SM7150_MASTER_VIDEO_PROC 53
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#define SM7150_SLAVE_A1NOC_CFG 54
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#define SM7150_SLAVE_A2NOC_CFG 55
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#define SM7150_SLAVE_AHB2PHY_NORTH 56
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#define SM7150_SLAVE_AHB2PHY_SOUTH 57
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#define SM7150_SLAVE_AHB2PHY_WEST 58
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#define SM7150_SLAVE_ANOC_PCIE_GEM_NOC 59
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#define SM7150_SLAVE_AOP 60
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#define SM7150_SLAVE_AOSS 61
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#define SM7150_SLAVE_APPSS 62
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#define SM7150_SLAVE_CAMERA_CFG 63
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#define SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG 64
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#define SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG 65
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#define SM7150_SLAVE_CAMNOC_UNCOMP 66
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#define SM7150_SLAVE_CDSP_CFG 67
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#define SM7150_SLAVE_CDSP_GEM_NOC 68
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#define SM7150_SLAVE_CLK_CTL 69
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#define SM7150_SLAVE_CNOC_A2NOC 70
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#define SM7150_SLAVE_CNOC_DDRSS 71
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#define SM7150_SLAVE_CNOC_MNOC_CFG 72
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#define SM7150_SLAVE_CRYPTO_0_CFG 73
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#define SM7150_SLAVE_DISPLAY_CFG 74
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#define SM7150_SLAVE_DISPLAY_THROTTLE_CFG 75
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#define SM7150_SLAVE_EBI_CH0 76
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#define SM7150_SLAVE_EMMC_CFG 77
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#define SM7150_SLAVE_GEM_NOC_CFG 78
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#define SM7150_SLAVE_GEM_NOC_SNOC 79
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#define SM7150_SLAVE_GLM 80
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#define SM7150_SLAVE_GRAPHICS_3D_CFG 81
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#define SM7150_SLAVE_IMEM_CFG 82
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#define SM7150_SLAVE_IPA_CFG 83
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#define SM7150_SLAVE_LLCC 84
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#define SM7150_SLAVE_LLCC_CFG 85
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#define SM7150_SLAVE_MNOC_HF_MEM_NOC 86
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#define SM7150_SLAVE_MNOC_SF_MEM_NOC 87
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#define SM7150_SLAVE_MSS_PROC_MS_MPU_CFG 88
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#define SM7150_SLAVE_OCIMEM 89
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#define SM7150_SLAVE_PCIE_CFG 90
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#define SM7150_SLAVE_PDM 91
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#define SM7150_SLAVE_PIMEM 92
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#define SM7150_SLAVE_PIMEM_CFG 93
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#define SM7150_SLAVE_PRNG 94
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#define SM7150_SLAVE_QDSS_CFG 95
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#define SM7150_SLAVE_QDSS_STM 96
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#define SM7150_SLAVE_QUP_0 97
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#define SM7150_SLAVE_QUP_1 98
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#define SM7150_SLAVE_RBCPR_CX_CFG 99
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#define SM7150_SLAVE_RBCPR_MX_CFG 100
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#define SM7150_SLAVE_SDCC_2 101
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#define SM7150_SLAVE_SDCC_4 102
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#define SM7150_SLAVE_SERVICE_A1NOC 103
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#define SM7150_SLAVE_SERVICE_A2NOC 104
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#define SM7150_SLAVE_SERVICE_CNOC 105
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#define SM7150_SLAVE_SERVICE_GEM_NOC 106
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#define SM7150_SLAVE_SERVICE_MNOC 107
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#define SM7150_SLAVE_SERVICE_SNOC 108
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#define SM7150_SLAVE_SNOC_CFG 109
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#define SM7150_SLAVE_SNOC_GEM_NOC_GC 110
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#define SM7150_SLAVE_SNOC_GEM_NOC_SF 111
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#define SM7150_SLAVE_SPDM_WRAPPER 112
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#define SM7150_SLAVE_TCSR 113
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#define SM7150_SLAVE_TCU 114
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#define SM7150_SLAVE_TLMM_NORTH 115
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#define SM7150_SLAVE_TLMM_SOUTH 116
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#define SM7150_SLAVE_TLMM_WEST 117
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#define SM7150_SLAVE_TSIF 118
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#define SM7150_SLAVE_UFS_MEM_CFG 119
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#define SM7150_SLAVE_USB3 120
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#define SM7150_SLAVE_VENUS_CFG 121
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#define SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG 122
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#define SM7150_SLAVE_VENUS_THROTTLE_CFG 123
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#define SM7150_SLAVE_VSENSE_CTRL_CFG 124
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#define SM7150_SNOC_CNOC_MAS 125
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#define SM7150_SNOC_CNOC_SLV 126
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#endif
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