80fd61ec46
Add clock definition and driver code for CV1800 SoC. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link:6f4e9b8ecb/duo/datasheet/CV180X-Clock-v1.xlsxLink:6f4e9b8ecb/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdfLink: https://lore.kernel.org/r/IA1PR20MB49534F37F802CAF117364D66BB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
67 lines
1.4 KiB
C
67 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
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*/
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/spinlock.h>
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#include <linux/bug.h>
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#include "clk-cv18xx-common.h"
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int cv1800_clk_setbit(struct cv1800_clk_common *common,
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struct cv1800_clk_regbit *field)
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{
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u32 mask = BIT(field->shift);
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u32 value;
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unsigned long flags;
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spin_lock_irqsave(common->lock, flags);
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value = readl(common->base + field->reg);
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writel(value | mask, common->base + field->reg);
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spin_unlock_irqrestore(common->lock, flags);
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return 0;
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}
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int cv1800_clk_clearbit(struct cv1800_clk_common *common,
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struct cv1800_clk_regbit *field)
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{
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u32 mask = BIT(field->shift);
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u32 value;
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unsigned long flags;
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spin_lock_irqsave(common->lock, flags);
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value = readl(common->base + field->reg);
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writel(value & ~mask, common->base + field->reg);
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spin_unlock_irqrestore(common->lock, flags);
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return 0;
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}
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int cv1800_clk_checkbit(struct cv1800_clk_common *common,
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struct cv1800_clk_regbit *field)
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{
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return readl(common->base + field->reg) & BIT(field->shift);
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}
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#define PLL_LOCK_TIMEOUT_US (200 * 1000)
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void cv1800_clk_wait_for_lock(struct cv1800_clk_common *common,
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u32 reg, u32 lock)
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{
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void __iomem *addr = common->base + reg;
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u32 regval;
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if (!lock)
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return;
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WARN_ON(readl_relaxed_poll_timeout(addr, regval, regval & lock,
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100, PLL_LOCK_TIMEOUT_US));
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}
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