1919d77a95
make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/mxc-clk.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/clk-imxrt1050.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240602-md-clk-imx-v1-1-5c6d240f6fab@quicinc.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
231 lines
5.1 KiB
C
231 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "clk.h"
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#define CCM_CCDR 0x4
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#define CCDR_MMDC_CH0_MASK BIT(17)
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#define CCDR_MMDC_CH1_MASK BIT(16)
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DEFINE_SPINLOCK(imx_ccm_lock);
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EXPORT_SYMBOL_GPL(imx_ccm_lock);
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bool mcore_booted;
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EXPORT_SYMBOL_GPL(mcore_booted);
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void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count)
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{
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unsigned int i;
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for (i = 0; i < count; i++)
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clk_hw_unregister(hws[i]);
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}
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EXPORT_SYMBOL_GPL(imx_unregister_hw_clocks);
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void imx_mmdc_mask_handshake(void __iomem *ccm_base,
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unsigned int chn)
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{
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unsigned int reg;
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reg = readl_relaxed(ccm_base + CCM_CCDR);
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reg |= chn == 0 ? CCDR_MMDC_CH0_MASK : CCDR_MMDC_CH1_MASK;
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writel_relaxed(reg, ccm_base + CCM_CCDR);
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}
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void imx_check_clocks(struct clk *clks[], unsigned int count)
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{
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unsigned i;
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for (i = 0; i < count; i++)
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if (IS_ERR(clks[i]))
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pr_err("i.MX clk %u: register failed with %ld\n",
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i, PTR_ERR(clks[i]));
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}
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void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
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{
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unsigned int i;
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for (i = 0; i < count; i++)
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if (IS_ERR(clks[i]))
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pr_err("i.MX clk %u: register failed with %ld\n",
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i, PTR_ERR(clks[i]));
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}
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EXPORT_SYMBOL_GPL(imx_check_clk_hws);
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static struct clk *imx_obtain_fixed_clock_from_dt(const char *name)
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{
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struct of_phandle_args phandle;
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struct clk *clk = ERR_PTR(-ENODEV);
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char *path;
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path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
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if (!path)
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return ERR_PTR(-ENOMEM);
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phandle.np = of_find_node_by_path(path);
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kfree(path);
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if (phandle.np) {
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clk = of_clk_get_from_provider(&phandle);
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of_node_put(phandle.np);
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}
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return clk;
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}
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struct clk *imx_obtain_fixed_clock(
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const char *name, unsigned long rate)
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{
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struct clk *clk;
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clk = imx_obtain_fixed_clock_from_dt(name);
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if (IS_ERR(clk))
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clk = imx_clk_fixed(name, rate);
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return clk;
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}
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struct clk_hw *imx_obtain_fixed_clock_hw(
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const char *name, unsigned long rate)
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{
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struct clk *clk;
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clk = imx_obtain_fixed_clock_from_dt(name);
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if (IS_ERR(clk))
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clk = imx_clk_fixed(name, rate);
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return __clk_get_hw(clk);
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}
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struct clk_hw *imx_obtain_fixed_of_clock(struct device_node *np,
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const char *name, unsigned long rate)
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{
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struct clk *clk = of_clk_get_by_name(np, name);
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struct clk_hw *hw;
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if (IS_ERR(clk))
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hw = imx_obtain_fixed_clock_hw(name, rate);
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else
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hw = __clk_get_hw(clk);
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return hw;
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}
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struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name)
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{
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struct clk *clk;
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clk = of_clk_get_by_name(np, name);
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if (IS_ERR(clk))
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return ERR_PTR(-ENOENT);
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return __clk_get_hw(clk);
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}
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EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name);
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/*
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* This fixups the register CCM_CSCMR1 write value.
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* The write/read/divider values of the aclk_podf field
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* of that register have the relationship described by
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* the following table:
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*
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* write value read value divider
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* 3b'000 3b'110 7
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* 3b'001 3b'111 8
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* 3b'010 3b'100 5
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* 3b'011 3b'101 6
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* 3b'100 3b'010 3
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* 3b'101 3b'011 4
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* 3b'110 3b'000 1
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* 3b'111 3b'001 2(default)
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*
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* That's why we do the xor operation below.
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*/
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#define CSCMR1_FIXUP 0x00600000
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void imx_cscmr1_fixup(u32 *val)
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{
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*val ^= CSCMR1_FIXUP;
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return;
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}
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#ifndef MODULE
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static bool imx_keep_uart_clocks;
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static int imx_enabled_uart_clocks;
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static struct clk **imx_uart_clocks;
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static int __init imx_keep_uart_clocks_param(char *str)
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{
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imx_keep_uart_clocks = 1;
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return 0;
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}
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__setup_param("earlycon", imx_keep_uart_earlycon,
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imx_keep_uart_clocks_param, 0);
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__setup_param("earlyprintk", imx_keep_uart_earlyprintk,
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imx_keep_uart_clocks_param, 0);
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void imx_register_uart_clocks(void)
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{
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unsigned int num __maybe_unused;
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imx_enabled_uart_clocks = 0;
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/* i.MX boards use device trees now. For build tests without CONFIG_OF, do nothing */
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#ifdef CONFIG_OF
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if (imx_keep_uart_clocks) {
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int i;
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num = of_clk_get_parent_count(of_stdout);
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if (!num)
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return;
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if (!of_stdout)
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return;
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imx_uart_clocks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL);
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if (!imx_uart_clocks)
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return;
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for (i = 0; i < num; i++) {
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imx_uart_clocks[imx_enabled_uart_clocks] = of_clk_get(of_stdout, i);
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/* Stop if there are no more of_stdout references */
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if (IS_ERR(imx_uart_clocks[imx_enabled_uart_clocks]))
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return;
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/* Only enable the clock if it's not NULL */
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if (imx_uart_clocks[imx_enabled_uart_clocks])
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clk_prepare_enable(imx_uart_clocks[imx_enabled_uart_clocks++]);
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}
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}
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#endif
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}
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static int __init imx_clk_disable_uart(void)
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{
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if (imx_keep_uart_clocks && imx_enabled_uart_clocks) {
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int i;
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for (i = 0; i < imx_enabled_uart_clocks; i++) {
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clk_disable_unprepare(imx_uart_clocks[i]);
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clk_put(imx_uart_clocks[i]);
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}
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}
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kfree(imx_uart_clocks);
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return 0;
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}
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late_initcall_sync(imx_clk_disable_uart);
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#endif
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MODULE_DESCRIPTION("Common clock support for NXP i.MX SoC family");
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MODULE_LICENSE("GPL v2");
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