0836c8604a
i.MX93 LPCG is different from i.MX8M CCGR. Although imx_clk_hw_gate4_flags is used here, it not strictly match i.MX93. i.MX93 has such design: - LPCG_DIRECT use BIT0 as on/off gate when LPCG_AUTHEN CPU_LPM is 0 - LPCG_LPM_CUR use BIT[2:0] as on/off gate when LPCG_AUTHEN CPU_LPM is 1 The current implementation suppose CPU_LPM is 0, and use LPCG_DIRECT BIT[1:0] as on/off gate. Although BIT1 is touched, actually BIT1 is reserved. And imx_clk_hw_gate4_flags use mask 0x3 to determine whether the clk is enabled or not, but i.MX93 LPCG only use BIT0 to control when CPU_LPM is 0. So clk disabled unused during kernel boot not able to gate off the unused clocks. To match i.MX93 LPCG, introduce imx93_clk_gate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220830033137.4149542-6-peng.fan@oss.nxp.com
200 lines
4.4 KiB
C
200 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define DIRECT_OFFSET 0x0
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/*
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* 0b000 - LPCG will be OFF in any CPU mode.
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* 0b100 - LPCG will be ON in any CPU mode.
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*/
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#define LPM_SETTING_OFF 0x0
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#define LPM_SETTING_ON 0x4
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#define LPM_CUR_OFFSET 0x1c
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#define AUTHEN_OFFSET 0x30
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#define CPULPM_EN BIT(2)
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#define TZ_NS_SHIFT 9
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#define TZ_NS_MASK BIT(9)
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#define WHITE_LIST_SHIFT 16
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struct imx93_clk_gate {
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struct clk_hw hw;
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void __iomem *reg;
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u32 bit_idx;
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u32 val;
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u32 mask;
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spinlock_t *lock;
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unsigned int *share_count;
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};
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#define to_imx93_clk_gate(_hw) container_of(_hw, struct imx93_clk_gate, hw)
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static void imx93_clk_gate_do_hardware(struct clk_hw *hw, bool enable)
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{
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struct imx93_clk_gate *gate = to_imx93_clk_gate(hw);
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u32 val;
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val = readl(gate->reg + AUTHEN_OFFSET);
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if (val & CPULPM_EN) {
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val = enable ? LPM_SETTING_ON : LPM_SETTING_OFF;
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writel(val, gate->reg + LPM_CUR_OFFSET);
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} else {
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val = readl(gate->reg + DIRECT_OFFSET);
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val &= ~(gate->mask << gate->bit_idx);
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if (enable)
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val |= (gate->val & gate->mask) << gate->bit_idx;
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writel(val, gate->reg + DIRECT_OFFSET);
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}
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}
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static int imx93_clk_gate_enable(struct clk_hw *hw)
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{
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struct imx93_clk_gate *gate = to_imx93_clk_gate(hw);
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unsigned long flags;
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spin_lock_irqsave(gate->lock, flags);
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if (gate->share_count && (*gate->share_count)++ > 0)
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goto out;
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imx93_clk_gate_do_hardware(hw, true);
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out:
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spin_unlock_irqrestore(gate->lock, flags);
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return 0;
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}
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static void imx93_clk_gate_disable(struct clk_hw *hw)
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{
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struct imx93_clk_gate *gate = to_imx93_clk_gate(hw);
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unsigned long flags;
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spin_lock_irqsave(gate->lock, flags);
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if (gate->share_count) {
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if (WARN_ON(*gate->share_count == 0))
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goto out;
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else if (--(*gate->share_count) > 0)
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goto out;
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}
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imx93_clk_gate_do_hardware(hw, false);
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out:
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static int imx93_clk_gate_reg_is_enabled(struct imx93_clk_gate *gate)
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{
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u32 val = readl(gate->reg + AUTHEN_OFFSET);
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if (val & CPULPM_EN) {
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val = readl(gate->reg + LPM_CUR_OFFSET);
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if (val == LPM_SETTING_ON)
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return 1;
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} else {
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val = readl(gate->reg);
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if (((val >> gate->bit_idx) & gate->mask) == gate->val)
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return 1;
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}
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return 0;
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}
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static int imx93_clk_gate_is_enabled(struct clk_hw *hw)
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{
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struct imx93_clk_gate *gate = to_imx93_clk_gate(hw);
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unsigned long flags;
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int ret;
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spin_lock_irqsave(gate->lock, flags);
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ret = imx93_clk_gate_reg_is_enabled(gate);
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spin_unlock_irqrestore(gate->lock, flags);
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return ret;
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}
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static void imx93_clk_gate_disable_unused(struct clk_hw *hw)
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{
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struct imx93_clk_gate *gate = to_imx93_clk_gate(hw);
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unsigned long flags;
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spin_lock_irqsave(gate->lock, flags);
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if (!gate->share_count || *gate->share_count == 0)
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imx93_clk_gate_do_hardware(hw, false);
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static const struct clk_ops imx93_clk_gate_ops = {
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.enable = imx93_clk_gate_enable,
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.disable = imx93_clk_gate_disable,
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.disable_unused = imx93_clk_gate_disable_unused,
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.is_enabled = imx93_clk_gate_is_enabled,
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};
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static const struct clk_ops imx93_clk_gate_ro_ops = {
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.is_enabled = imx93_clk_gate_is_enabled,
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};
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struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name,
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unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val,
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u32 mask, u32 domain_id, unsigned int *share_count)
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{
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struct imx93_clk_gate *gate;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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u32 authen;
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gate = kzalloc(sizeof(struct imx93_clk_gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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gate->reg = reg;
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gate->lock = &imx_ccm_lock;
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gate->bit_idx = bit_idx;
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gate->val = val;
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gate->mask = mask;
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gate->share_count = share_count;
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init.name = name;
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init.ops = &imx93_clk_gate_ops;
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init.flags = flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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gate->hw.init = &init;
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hw = &gate->hw;
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authen = readl(reg + AUTHEN_OFFSET);
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if (!(authen & TZ_NS_MASK) || !(authen & BIT(WHITE_LIST_SHIFT + domain_id)))
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init.ops = &imx93_clk_gate_ro_ops;
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ret = clk_hw_register(dev, hw);
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if (ret) {
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kfree(gate);
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return ERR_PTR(ret);
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}
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return hw;
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}
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EXPORT_SYMBOL_GPL(imx93_clk_gate);
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