f00b45db02
After commit 0edb555a65
("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.
Convert all clk drivers to use .remove(), with the eventual goal to drop
struct platform_driver::remove_new(). As .remove() and .remove_new() have
the same prototypes, conversion is done by just changing the structure
member name in the driver initializer.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
203 lines
5.3 KiB
C
203 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Hi3519 Clock Driver
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*
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* Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
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*/
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#include <dt-bindings/clock/hi3519-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk.h"
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#include "reset.h"
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#define HI3519_INNER_CLK_OFFSET 64
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#define HI3519_FIXED_24M 65
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#define HI3519_FIXED_50M 66
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#define HI3519_FIXED_75M 67
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#define HI3519_FIXED_125M 68
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#define HI3519_FIXED_150M 69
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#define HI3519_FIXED_200M 70
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#define HI3519_FIXED_250M 71
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#define HI3519_FIXED_300M 72
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#define HI3519_FIXED_400M 73
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#define HI3519_FMC_MUX 74
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#define HI3519_NR_CLKS 128
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struct hi3519_crg_data {
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struct hisi_clock_data *clk_data;
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struct hisi_reset_controller *rstc;
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};
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static const struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] = {
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{ HI3519_FIXED_24M, "24m", NULL, 0, 24000000, },
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{ HI3519_FIXED_50M, "50m", NULL, 0, 50000000, },
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{ HI3519_FIXED_75M, "75m", NULL, 0, 75000000, },
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{ HI3519_FIXED_125M, "125m", NULL, 0, 125000000, },
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{ HI3519_FIXED_150M, "150m", NULL, 0, 150000000, },
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{ HI3519_FIXED_200M, "200m", NULL, 0, 200000000, },
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{ HI3519_FIXED_250M, "250m", NULL, 0, 250000000, },
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{ HI3519_FIXED_300M, "300m", NULL, 0, 300000000, },
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{ HI3519_FIXED_400M, "400m", NULL, 0, 400000000, },
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};
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static const char *const fmc_mux_p[] = {
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"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
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static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
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static const struct hisi_mux_clock hi3519_mux_clks[] = {
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{ HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
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CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
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};
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static const struct hisi_gate_clock hi3519_gate_clks[] = {
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{ HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
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CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
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{ HI3519_UART0_CLK, "clk_uart0", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
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{ HI3519_UART1_CLK, "clk_uart1", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
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{ HI3519_UART2_CLK, "clk_uart2", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
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{ HI3519_UART3_CLK, "clk_uart3", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
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{ HI3519_UART4_CLK, "clk_uart4", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
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{ HI3519_SPI0_CLK, "clk_spi0", "50m",
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CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
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{ HI3519_SPI1_CLK, "clk_spi1", "50m",
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CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
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{ HI3519_SPI2_CLK, "clk_spi2", "50m",
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CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
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};
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static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev)
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{
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struct hisi_clock_data *clk_data;
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int ret;
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clk_data = hisi_clk_alloc(pdev, HI3519_NR_CLKS);
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if (!clk_data)
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return ERR_PTR(-ENOMEM);
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ret = hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
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ARRAY_SIZE(hi3519_fixed_rate_clks),
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clk_data);
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if (ret)
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return ERR_PTR(ret);
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ret = hisi_clk_register_mux(hi3519_mux_clks,
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ARRAY_SIZE(hi3519_mux_clks),
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clk_data);
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if (ret)
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goto unregister_fixed_rate;
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ret = hisi_clk_register_gate(hi3519_gate_clks,
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ARRAY_SIZE(hi3519_gate_clks),
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clk_data);
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if (ret)
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goto unregister_mux;
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ret = of_clk_add_provider(pdev->dev.of_node,
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of_clk_src_onecell_get, &clk_data->clk_data);
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if (ret)
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goto unregister_gate;
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return clk_data;
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unregister_fixed_rate:
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hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
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ARRAY_SIZE(hi3519_fixed_rate_clks),
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clk_data);
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unregister_mux:
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hisi_clk_unregister_mux(hi3519_mux_clks,
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ARRAY_SIZE(hi3519_mux_clks),
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clk_data);
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unregister_gate:
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hisi_clk_unregister_gate(hi3519_gate_clks,
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ARRAY_SIZE(hi3519_gate_clks),
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clk_data);
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return ERR_PTR(ret);
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}
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static void hi3519_clk_unregister(struct platform_device *pdev)
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{
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struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
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of_clk_del_provider(pdev->dev.of_node);
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hisi_clk_unregister_gate(hi3519_gate_clks,
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ARRAY_SIZE(hi3519_gate_clks),
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crg->clk_data);
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hisi_clk_unregister_mux(hi3519_mux_clks,
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ARRAY_SIZE(hi3519_mux_clks),
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crg->clk_data);
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hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
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ARRAY_SIZE(hi3519_fixed_rate_clks),
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crg->clk_data);
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}
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static int hi3519_clk_probe(struct platform_device *pdev)
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{
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struct hi3519_crg_data *crg;
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crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
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if (!crg)
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return -ENOMEM;
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crg->rstc = hisi_reset_init(pdev);
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if (!crg->rstc)
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return -ENOMEM;
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crg->clk_data = hi3519_clk_register(pdev);
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if (IS_ERR(crg->clk_data)) {
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hisi_reset_exit(crg->rstc);
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return PTR_ERR(crg->clk_data);
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}
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platform_set_drvdata(pdev, crg);
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return 0;
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}
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static void hi3519_clk_remove(struct platform_device *pdev)
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{
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struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
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hisi_reset_exit(crg->rstc);
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hi3519_clk_unregister(pdev);
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}
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static const struct of_device_id hi3519_clk_match_table[] = {
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{ .compatible = "hisilicon,hi3519-crg" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, hi3519_clk_match_table);
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static struct platform_driver hi3519_clk_driver = {
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.probe = hi3519_clk_probe,
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.remove = hi3519_clk_remove,
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.driver = {
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.name = "hi3519-clk",
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.of_match_table = hi3519_clk_match_table,
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},
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};
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static int __init hi3519_clk_init(void)
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{
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return platform_driver_register(&hi3519_clk_driver);
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}
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core_initcall(hi3519_clk_init);
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static void __exit hi3519_clk_exit(void)
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{
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platform_driver_unregister(&hi3519_clk_driver);
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}
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module_exit(hi3519_clk_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver");
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