965e063743
i.MX95 System Management Control Firmware(SCMI) manages the clock function, it exposes PLL VCO which could support up to 5GHz rate that exceeds UINT32_MAX. So add assigned-clock-rates-u64 support to set rate that exceeds UINT32_MAX. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240804-clk-u64-v4-2-8e55569f39a4@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
184 lines
4.6 KiB
C
184 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014 Samsung Electronics Co., Ltd.
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* Sylwester Nawrocki <s.nawrocki@samsung.com>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/clk-conf.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/printk.h>
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#include <linux/slab.h>
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static int __set_clk_parents(struct device_node *node, bool clk_supplier)
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{
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struct of_phandle_args clkspec;
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int index, rc, num_parents;
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struct clk *clk, *pclk;
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num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
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"#clock-cells");
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if (num_parents == -EINVAL)
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pr_err("clk: invalid value of clock-parents property at %pOF\n",
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node);
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for (index = 0; index < num_parents; index++) {
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rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
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"#clock-cells", index, &clkspec);
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if (rc < 0) {
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/* skip empty (null) phandles */
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if (rc == -ENOENT)
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continue;
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else
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return rc;
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}
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if (clkspec.np == node && !clk_supplier) {
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of_node_put(clkspec.np);
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return 0;
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}
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pclk = of_clk_get_from_provider(&clkspec);
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of_node_put(clkspec.np);
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if (IS_ERR(pclk)) {
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if (PTR_ERR(pclk) != -EPROBE_DEFER)
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pr_warn("clk: couldn't get parent clock %d for %pOF\n",
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index, node);
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return PTR_ERR(pclk);
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}
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rc = of_parse_phandle_with_args(node, "assigned-clocks",
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"#clock-cells", index, &clkspec);
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if (rc < 0)
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goto err;
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if (clkspec.np == node && !clk_supplier) {
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of_node_put(clkspec.np);
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rc = 0;
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goto err;
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}
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clk = of_clk_get_from_provider(&clkspec);
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of_node_put(clkspec.np);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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pr_warn("clk: couldn't get assigned clock %d for %pOF\n",
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index, node);
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rc = PTR_ERR(clk);
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goto err;
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}
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rc = clk_set_parent(clk, pclk);
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if (rc < 0)
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pr_err("clk: failed to reparent %s to %s: %d\n",
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__clk_get_name(clk), __clk_get_name(pclk), rc);
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clk_put(clk);
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clk_put(pclk);
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}
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return 0;
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err:
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clk_put(pclk);
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return rc;
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}
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static int __set_clk_rates(struct device_node *node, bool clk_supplier)
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{
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struct of_phandle_args clkspec;
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int rc, count, count_64, index;
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struct clk *clk;
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u64 *rates_64 __free(kfree) = NULL;
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u32 *rates __free(kfree) = NULL;
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count = of_property_count_u32_elems(node, "assigned-clock-rates");
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count_64 = of_property_count_u64_elems(node, "assigned-clock-rates-u64");
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if (count_64 > 0) {
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count = count_64;
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rates_64 = kcalloc(count, sizeof(*rates_64), GFP_KERNEL);
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if (!rates_64)
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return -ENOMEM;
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rc = of_property_read_u64_array(node,
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"assigned-clock-rates-u64",
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rates_64, count);
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} else if (count > 0) {
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rates = kcalloc(count, sizeof(*rates), GFP_KERNEL);
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if (!rates)
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return -ENOMEM;
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rc = of_property_read_u32_array(node, "assigned-clock-rates",
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rates, count);
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} else {
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return 0;
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}
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if (rc)
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return rc;
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for (index = 0; index < count; index++) {
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unsigned long rate;
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if (rates_64)
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rate = rates_64[index];
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else
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rate = rates[index];
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if (rate) {
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rc = of_parse_phandle_with_args(node, "assigned-clocks",
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"#clock-cells", index, &clkspec);
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if (rc < 0) {
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/* skip empty (null) phandles */
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if (rc == -ENOENT)
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continue;
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else
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return rc;
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}
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if (clkspec.np == node && !clk_supplier) {
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of_node_put(clkspec.np);
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return 0;
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}
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clk = of_clk_get_from_provider(&clkspec);
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of_node_put(clkspec.np);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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pr_warn("clk: couldn't get clock %d for %pOF\n",
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index, node);
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return PTR_ERR(clk);
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}
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rc = clk_set_rate(clk, rate);
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if (rc < 0)
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pr_err("clk: couldn't set %s clk rate to %lu (%d), current rate: %lu\n",
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__clk_get_name(clk), rate, rc,
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clk_get_rate(clk));
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clk_put(clk);
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}
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}
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return 0;
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}
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/**
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* of_clk_set_defaults() - parse and set assigned clocks configuration
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* @node: device node to apply clock settings for
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* @clk_supplier: true if clocks supplied by @node should also be considered
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*
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* This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties
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* and sets any specified clock parents and rates. The @clk_supplier argument
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* should be set to true if @node may be also a clock supplier of any clock
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* listed in its 'assigned-clocks' or 'assigned-clock-parents' properties.
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* If @clk_supplier is false the function exits returning 0 as soon as it
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* determines the @node is also a supplier of any of the clocks.
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*/
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int of_clk_set_defaults(struct device_node *node, bool clk_supplier)
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{
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int rc;
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if (!node)
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return 0;
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rc = __set_clk_parents(node, clk_supplier);
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if (rc < 0)
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return rc;
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return __set_clk_rates(node, clk_supplier);
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}
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EXPORT_SYMBOL_GPL(of_clk_set_defaults);
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