75ded18a5e
Add LSX and LASX implementations of xor operations, operating on 64 bytes (one L1 cache line) at a time, for a balance between memory utilization and instruction mix. Huacai confirmed that all future LoongArch implementations by Loongson (that we care) will likely also feature 64-byte cache lines, and experiments show no throughput improvement with further unrolling. Performance numbers measured during system boot on a 3A5000 @ 2.5GHz: > 8regs : 12702 MB/sec > 8regs_prefetch : 10920 MB/sec > 32regs : 12686 MB/sec > 32regs_prefetch : 10918 MB/sec > lsx : 17589 MB/sec > lasx : 26116 MB/sec Acked-by: Song Liu <song@kernel.org> Signed-off-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
39 lines
1.8 KiB
C
39 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Simple interface to link xor_simd.c and xor_simd_glue.c
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*
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* Separating these files ensures that no SIMD instructions are run outside of
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* the kfpu critical section.
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*/
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#ifndef __LOONGARCH_LIB_XOR_SIMD_H
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#define __LOONGARCH_LIB_XOR_SIMD_H
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#ifdef CONFIG_CPU_HAS_LSX
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void __xor_lsx_2(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2);
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void __xor_lsx_3(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2, const unsigned long * __restrict p3);
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void __xor_lsx_4(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2, const unsigned long * __restrict p3,
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const unsigned long * __restrict p4);
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void __xor_lsx_5(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2, const unsigned long * __restrict p3,
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const unsigned long * __restrict p4, const unsigned long * __restrict p5);
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#endif /* CONFIG_CPU_HAS_LSX */
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#ifdef CONFIG_CPU_HAS_LASX
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void __xor_lasx_2(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2);
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void __xor_lasx_3(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2, const unsigned long * __restrict p3);
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void __xor_lasx_4(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2, const unsigned long * __restrict p3,
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const unsigned long * __restrict p4);
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void __xor_lasx_5(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2, const unsigned long * __restrict p3,
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const unsigned long * __restrict p4, const unsigned long * __restrict p5);
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#endif /* CONFIG_CPU_HAS_LASX */
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#endif /* __LOONGARCH_LIB_XOR_SIMD_H */
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