d352264867
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
167 lines
3.1 KiB
C
167 lines
3.1 KiB
C
/* Blackfin KGDB header
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*
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* Copyright 2005-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __ASM_BLACKFIN_KGDB_H__
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#define __ASM_BLACKFIN_KGDB_H__
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#include <linux/ptrace.h>
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/* gdb locks */
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#define KGDB_MAX_NO_CPUS 8
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/*
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* BUFMAX defines the maximum number of characters in inbound/outbound buffers.
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* At least NUMREGBYTES*2 are needed for register packets.
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* Longer buffer is needed to list all threads.
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*/
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#define BUFMAX 2048
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/*
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* Note that this register image is different from
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* the register image that Linux produces at interrupt time.
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*
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* Linux's register image is defined by struct pt_regs in ptrace.h.
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*/
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enum regnames {
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/* Core Registers */
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BFIN_R0 = 0,
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BFIN_R1,
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BFIN_R2,
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BFIN_R3,
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BFIN_R4,
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BFIN_R5,
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BFIN_R6,
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BFIN_R7,
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BFIN_P0,
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BFIN_P1,
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BFIN_P2,
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BFIN_P3,
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BFIN_P4,
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BFIN_P5,
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BFIN_SP,
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BFIN_FP,
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BFIN_I0,
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BFIN_I1,
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BFIN_I2,
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BFIN_I3,
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BFIN_M0,
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BFIN_M1,
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BFIN_M2,
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BFIN_M3,
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BFIN_B0,
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BFIN_B1,
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BFIN_B2,
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BFIN_B3,
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BFIN_L0,
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BFIN_L1,
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BFIN_L2,
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BFIN_L3,
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BFIN_A0_DOT_X,
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BFIN_A0_DOT_W,
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BFIN_A1_DOT_X,
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BFIN_A1_DOT_W,
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BFIN_ASTAT,
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BFIN_RETS,
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BFIN_LC0,
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BFIN_LT0,
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BFIN_LB0,
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BFIN_LC1,
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BFIN_LT1,
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BFIN_LB1,
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BFIN_CYCLES,
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BFIN_CYCLES2,
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BFIN_USP,
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BFIN_SEQSTAT,
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BFIN_SYSCFG,
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BFIN_RETI,
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BFIN_RETX,
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BFIN_RETN,
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BFIN_RETE,
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/* Pseudo Registers */
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BFIN_PC,
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BFIN_CC,
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BFIN_EXTRA1, /* Address of .text section. */
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BFIN_EXTRA2, /* Address of .data section. */
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BFIN_EXTRA3, /* Address of .bss section. */
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BFIN_FDPIC_EXEC,
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BFIN_FDPIC_INTERP,
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/* MMRs */
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BFIN_IPEND,
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/* LAST ENTRY SHOULD NOT BE CHANGED. */
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BFIN_NUM_REGS /* The number of all registers. */
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};
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/* Number of bytes of registers. */
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#define NUMREGBYTES BFIN_NUM_REGS*4
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static inline void arch_kgdb_breakpoint(void)
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{
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asm("EXCPT 2;");
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}
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#define BREAK_INSTR_SIZE 2
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#define CACHE_FLUSH_IS_SAFE 1
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#define HW_INST_WATCHPOINT_NUM 6
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#define HW_WATCHPOINT_NUM 8
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#define TYPE_INST_WATCHPOINT 0
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#define TYPE_DATA_WATCHPOINT 1
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/* Instruction watchpoint address control register bits mask */
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#define WPPWR 0x1
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#define WPIREN01 0x2
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#define WPIRINV01 0x4
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#define WPIAEN0 0x8
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#define WPIAEN1 0x10
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#define WPICNTEN0 0x20
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#define WPICNTEN1 0x40
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#define EMUSW0 0x80
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#define EMUSW1 0x100
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#define WPIREN23 0x200
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#define WPIRINV23 0x400
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#define WPIAEN2 0x800
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#define WPIAEN3 0x1000
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#define WPICNTEN2 0x2000
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#define WPICNTEN3 0x4000
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#define EMUSW2 0x8000
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#define EMUSW3 0x10000
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#define WPIREN45 0x20000
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#define WPIRINV45 0x40000
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#define WPIAEN4 0x80000
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#define WPIAEN5 0x100000
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#define WPICNTEN4 0x200000
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#define WPICNTEN5 0x400000
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#define EMUSW4 0x800000
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#define EMUSW5 0x1000000
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#define WPAND 0x2000000
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/* Data watchpoint address control register bits mask */
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#define WPDREN01 0x1
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#define WPDRINV01 0x2
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#define WPDAEN0 0x4
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#define WPDAEN1 0x8
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#define WPDCNTEN0 0x10
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#define WPDCNTEN1 0x20
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#define WPDSRC0 0xc0
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#define WPDACC0_OFFSET 8
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#define WPDSRC1 0xc00
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#define WPDACC1_OFFSET 12
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/* Watchpoint status register bits mask */
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#define STATIA0 0x1
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#define STATIA1 0x2
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#define STATIA2 0x4
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#define STATIA3 0x8
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#define STATIA4 0x10
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#define STATIA5 0x20
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#define STATDA0 0x40
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#define STATDA1 0x80
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#endif
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