41ba653f24
The current cache options don't really represent the hardware features. They end up setting different aspects of the hardware so that the end result is to turn on/off the cache. Unfortunately, when we hit cache problems with the hardware, it's difficult to test different settings to root cause the problem. The current settings also don't cleanly allow for different caching behaviors with different regions of memory. So split the configure options such that they properly reflect the settings that are applied to the hardware. Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
64 lines
1.3 KiB
C
64 lines
1.3 KiB
C
/*
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* include/asm-blackfin/cache.h
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*/
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#ifndef __ARCH_BLACKFIN_CACHE_H
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#define __ARCH_BLACKFIN_CACHE_H
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/*
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* Bytes per L1 cache line
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* Blackfin loads 32 bytes for cache
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*/
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#ifdef CONFIG_SMP
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#define __cacheline_aligned
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#else
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#define ____cacheline_aligned
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/*
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* Put cacheline_aliged data to L1 data memory
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*/
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#ifdef CONFIG_CACHELINE_ALIGNED_L1
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#define __cacheline_aligned \
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__attribute__((__aligned__(L1_CACHE_BYTES), \
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__section__(".data_l1.cacheline_aligned")))
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#endif
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#endif
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/*
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* largest L1 which this arch supports
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*/
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#define L1_CACHE_SHIFT_MAX 5
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#if defined(CONFIG_SMP) && \
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!defined(CONFIG_BFIN_CACHE_COHERENT)
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# if defined(CONFIG_BFIN_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
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# define __ARCH_SYNC_CORE_ICACHE
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# endif
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# if defined(CONFIG_BFIN_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
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# define __ARCH_SYNC_CORE_DCACHE
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# endif
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#ifndef __ASSEMBLY__
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asmlinkage void __raw_smp_mark_barrier_asm(void);
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asmlinkage void __raw_smp_check_barrier_asm(void);
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static inline void smp_mark_barrier(void)
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{
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__raw_smp_mark_barrier_asm();
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}
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static inline void smp_check_barrier(void)
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{
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__raw_smp_check_barrier_asm();
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}
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void resync_core_dcache(void);
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void resync_core_icache(void);
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#endif
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#endif
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#endif
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