2295196c30
Patch from Marc Singer Updates to the lpd7a40x platform headers. Includes support for new architecture, lpd7a400. Signed-off-by: Marc Singer <elf@buici.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
347 lines
8.3 KiB
C
347 lines
8.3 KiB
C
/* lcd-panel.h
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$Id$
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written by Marc Singer
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18 Jul 2005
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Copyright (C) 2005 Marc Singer
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-----------
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DESCRIPTION
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-----------
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Only one panel may be defined at a time.
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The pixel clock is calculated to be no greater than the target.
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Each timing value is accompanied by a specification comment.
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UNITS/MIN/TYP/MAX
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Most of the units will be in clocks.
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USE_RGB555
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Define this macro to configure the AMBA LCD controller to use an
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RGB555 encoding for the pels instead of the normal RGB565.
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LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11
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These boards are best approximated by 555 for all panels. Some
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can use an extra low-order bit of blue in bit 16 of the color
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value, but we don't have a way to communicate this non-linear
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mapping to the kernel.
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*/
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#if !defined (__LCD_PANEL_H__)
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# define __LCD_PANEL_H__
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#if defined (MACH_LPD79520)\
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|| defined (MACH_LPD79524)\
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|| defined (MACH_LPD7A400)\
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|| defined (MACH_LPD7A404)
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# define USE_RGB555
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#endif
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struct clcd_panel_extra {
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unsigned int hrmode;
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unsigned int clsen;
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unsigned int spsen;
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unsigned int pcdel;
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unsigned int revdel;
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unsigned int lpdel;
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unsigned int spldel;
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unsigned int pc2del;
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};
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#define NS_TO_CLOCK(ns,c) ((((ns)*((c)/1000) + (1000000 - 1))/1000000))
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#define CLOCK_TO_DIV(e,c) (((c) + (e) - 1)/(e))
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#if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
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/* Logic Product Development LCD 3.5" QVGA HRTFT -10 */
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/* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */
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#define PIX_CLOCK_TARGET (6800000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "3.5in QVGA (LQ035Q7DB02)",
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.xres = 240,
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.yres = 320,
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.pixclock = PIX_CLOCK,
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.left_margin = 16,
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.right_margin = 21,
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.upper_margin = 8, // line/8/8/8
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.lower_margin = 5,
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.hsync_len = 61,
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.vsync_len = NS_TO_CLOCK (60, PIX_CLOCK),
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#define HAS_LCD_PANEL_EXTRA
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static struct clcd_panel_extra lcd_panel_extra = {
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.hrmode = 1,
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.clsen = 1,
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.spsen = 1,
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.pcdel = 8,
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.revdel = 7,
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.lpdel = 13,
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.spldel = 77,
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.pc2del = 208,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02
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/* Logic Product Development LCD 5.7" QVGA -10 */
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/* Sharp PN LQ057Q3DC02 */
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/* QVGA mode, V/Q=LOW */
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/* From Sharp on 2006.1.3. I believe some of the values are incorrect
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* based on the datasheet.
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Timing0 TIMING1 TIMING2 CONTROL
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0x140A0C4C 0x080504EF 0x013F380D 0x00000829
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HBP= 20 VBP= 8 BCD= 0
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HFP= 10 VFP= 5 CPL=319
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HSW= 12 VSW= 1 IOE= 0
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PPL= 19 LPP=239 IPC= 1
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IHS= 1
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IVS= 1
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ACB= 0
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CSEL= 0
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PCD= 13
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*/
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/* The full horozontal cycle (Th) is clock/360/400/450. */
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/* The full vertical cycle (Tv) is line/251/262/280. */
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#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "5.7in QVGA (LQ057Q3DC02)",
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.xres = 320,
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.yres = 240,
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.pixclock = PIX_CLOCK,
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.left_margin = 11,
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.right_margin = 400-11-320-2,
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.upper_margin = 7, // line/7/7/7
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.lower_margin = 262-7-240-2,
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.hsync_len = 2, // clk/2/96/200
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.vsync_len = 2, // line/2/-/34
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343
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/* Logic Product Development LCD 6.4" VGA -10 */
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/* Sharp PN LQ64D343 */
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/* The full horozontal cycle (Th) is clock/750/800/900. */
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/* The full vertical cycle (Tv) is line/515/525/560. */
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#define PIX_CLOCK_TARGET (28330000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "6.4in QVGA (LQ64D343)",
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.xres = 640,
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.yres = 480,
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.pixclock = PIX_CLOCK,
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.left_margin = 32,
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.right_margin = 800-32-640-96,
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.upper_margin = 32, // line/34/34/34
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.lower_margin = 540-32-480-2,
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.hsync_len = 96, // clk/2/96/200
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.vsync_len = 2, // line/2/-/34
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368
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/* Logic Product Development LCD 10.4" VGA -10 */
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/* Sharp PN LQ10D368 */
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#define PIX_CLOCK_TARGET (28330000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "10.4in VGA (LQ10D368)",
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.xres = 640,
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.yres = 480,
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.pixclock = PIX_CLOCK,
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.left_margin = 21,
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.right_margin = 15,
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.upper_margin = 34,
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.lower_margin = 5,
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.hsync_len = 96,
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.vsync_len = 16,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41
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/* Logic Product Development LCD 12.1" SVGA -10 */
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/* Sharp PN LQ121S1DG41, was LQ121S1DG31 */
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/* Note that with a 99993900 Hz HCLK, it is not possible to hit the
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* target clock frequency range of 35MHz to 42MHz. */
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/* If the target pixel clock is substantially lower than the panel
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* spec, this is done to prevent the LCD display from glitching when
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* the CPU is under load. A pixel clock higher than 25MHz
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* (empirically determined) will compete with the CPU for bus cycles
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* for the Ethernet chip. However, even a pixel clock of 10MHz
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* competes with Compact Flash interface during some operations
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* (fdisk, e2fsck). And, at that speed the display may have a visible
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* flicker. */
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/* The full horozontal cycle (Th) is clock/832/1056/1395. */
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#define PIX_CLOCK_TARGET (20000000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "12.1in SVGA (LQ121S1DG41)",
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.xres = 800,
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.yres = 600,
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.pixclock = PIX_CLOCK,
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.left_margin = 89, // ns/5/-/(1/PIX_CLOCK)-10
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.right_margin = 1056-800-89-128,
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.upper_margin = 23, // line/23/23/23
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.lower_margin = 44,
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.hsync_len = 128, // clk/2/128/200
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.vsync_len = 4, // line/2/4/6
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_HITACHI
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/* Hitachi*/
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/* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
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#define PIX_CLOCK_TARGET (49000000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "Hitachi 800x480",
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.xres = 800,
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.yres = 480,
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.pixclock = PIX_CLOCK,
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.left_margin = 88,
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.right_margin = 40,
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.upper_margin = 32,
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.lower_margin = 11,
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.hsync_len = 128,
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.vsync_len = 2,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE
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/* AU Optotronics A070VW01 7.0 Wide Screen color Display*/
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/* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
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#define PIX_CLOCK_TARGET (10000000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "7.0in Wide (A070VW01)",
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.xres = 480,
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.yres = 234,
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.pixclock = PIX_CLOCK,
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.left_margin = 30,
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.right_margin = 25,
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.upper_margin = 14,
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.lower_margin = 12,
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.hsync_len = 100,
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.vsync_len = 1,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#undef NS_TO_CLOCK
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#undef CLOCK_TO_DIV
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#endif /* __LCD_PANEL_H__ */
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