c9749a3523
When L1 cache is suppose to be lost, it needs to be cleaned before entrering to the low power mode. While at this, also fix few comments and remove un-necessary clean_l2 lable. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
802 lines
21 KiB
ArmAsm
802 lines
21 KiB
ArmAsm
/*
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* (C) Copyright 2007
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* Texas Instruments
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* Karthik Dasu <karthik-dp@ti.com>
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*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <plat/sram.h>
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#include <mach/io.h>
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#include "cm2xxx_3xxx.h"
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#include "prm2xxx_3xxx.h"
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#include "sdrc.h"
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#include "control.h"
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/*
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* Registers access definitions
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*/
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#define SDRC_SCRATCHPAD_SEM_OFFS 0xc
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#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\
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(SDRC_SCRATCHPAD_SEM_OFFS)
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#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
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OMAP3430_PM_PREPWSTST
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#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
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#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
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#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
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#define SRAM_BASE_P OMAP3_SRAM_PA
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#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
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#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
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OMAP36XX_CONTROL_MEM_RTA_CTRL)
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/* Move this as correct place is available */
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#define SCRATCHPAD_MEM_OFFS 0x310
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#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
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OMAP343X_CONTROL_MEM_WKUP +\
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SCRATCHPAD_MEM_OFFS)
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#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
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#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
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#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
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#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
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#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
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#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
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#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
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#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
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#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
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#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
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/*
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* This file needs be built unconditionally as ARM to interoperate correctly
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* with non-Thumb-2-capable firmware.
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*/
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.arm
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/*
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* API functions
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*/
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/*
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* The "get_*restore_pointer" functions are used to provide a
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* physical restore address where the ROM code jumps while waking
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* up from MPU OFF/OSWR state.
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* The restore pointer is stored into the scratchpad.
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*/
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.text
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/* Function call to get the restore pointer for resume from OFF */
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ENTRY(get_restore_pointer)
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stmfd sp!, {lr} @ save registers on stack
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adr r0, restore
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ldmfd sp!, {pc} @ restore regs and return
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ENDPROC(get_restore_pointer)
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.align
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ENTRY(get_restore_pointer_sz)
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.word . - get_restore_pointer
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.text
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/* Function call to get the restore pointer for 3630 resume from OFF */
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ENTRY(get_omap3630_restore_pointer)
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stmfd sp!, {lr} @ save registers on stack
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adr r0, restore_3630
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ldmfd sp!, {pc} @ restore regs and return
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ENDPROC(get_omap3630_restore_pointer)
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.align
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ENTRY(get_omap3630_restore_pointer_sz)
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.word . - get_omap3630_restore_pointer
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.text
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/* Function call to get the restore pointer for ES3 to resume from OFF */
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ENTRY(get_es3_restore_pointer)
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stmfd sp!, {lr} @ save registers on stack
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adr r0, restore_es3
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ldmfd sp!, {pc} @ restore regs and return
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ENDPROC(get_es3_restore_pointer)
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.align
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ENTRY(get_es3_restore_pointer_sz)
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.word . - get_es3_restore_pointer
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.text
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/*
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* L2 cache needs to be toggled for stable OFF mode functionality on 3630.
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* This function sets up a flag that will allow for this toggling to take
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* place on 3630. Hopefully some version in the future may not need this.
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*/
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ENTRY(enable_omap3630_toggle_l2_on_restore)
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stmfd sp!, {lr} @ save registers on stack
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/* Setup so that we will disable and enable l2 */
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mov r1, #0x1
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adrl r2, l2dis_3630 @ may be too distant for plain adr
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str r1, [r2]
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ldmfd sp!, {pc} @ restore regs and return
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ENDPROC(enable_omap3630_toggle_l2_on_restore)
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.text
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/* Function to call rom code to save secure ram context */
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ENTRY(save_secure_ram_context)
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stmfd sp!, {r1-r12, lr} @ save registers on stack
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adr r3, api_params @ r3 points to parameters
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str r0, [r3,#0x4] @ r0 has sdram address
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ldr r12, high_mask
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and r3, r3, r12
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ldr r12, sram_phy_addr_mask
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orr r3, r3, r12
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mov r0, #25 @ set service ID for PPA
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mov r12, r0 @ copy secure service ID in r12
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mov r1, #0 @ set task id for ROM code in r1
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mov r2, #4 @ set some flags in r2, r6
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mov r6, #0xff
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dsb @ data write barrier
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dmb @ data memory barrier
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smc #1 @ call SMI monitor (smi #1)
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nop
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nop
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nop
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nop
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ldmfd sp!, {r1-r12, pc}
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.align
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sram_phy_addr_mask:
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.word SRAM_BASE_P
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high_mask:
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.word 0xffff
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api_params:
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.word 0x4, 0x0, 0x0, 0x1, 0x1
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ENDPROC(save_secure_ram_context)
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ENTRY(save_secure_ram_context_sz)
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.word . - save_secure_ram_context
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/*
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* ======================
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* == Idle entry point ==
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* ======================
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*/
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/*
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* Forces OMAP into idle state
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*
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* omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
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* and executes the WFI instruction. Calling WFI effectively changes the
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* power domains states to the desired target power states.
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*
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*
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* Notes:
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* - this code gets copied to internal SRAM at boot and after wake-up
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* from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
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* - when the OMAP wakes up it continues at different execution points
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* depending on the low power mode (non-OFF vs OFF modes),
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* cf. 'Resume path for xxx mode' comments.
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*/
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ENTRY(omap34xx_cpu_suspend)
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stmfd sp!, {r0-r12, lr} @ save registers on stack
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/*
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* r0 contains CPU context save/restore pointer in sdram
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* r1 contains information about saving context:
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* 0 - No context lost
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* 1 - Only L1 and logic lost
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* 2 - Only L2 lost (Even L1 is retained we clean it along with L2)
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* 3 - Both L1 and L2 lost and logic lost
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*/
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/* Directly jump to WFI is the context save is not required */
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cmp r1, #0x0
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beq omap3_do_wfi
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/* Otherwise fall through to the save context code */
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save_context_wfi:
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mov r8, r0 @ Store SDRAM address in r8
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mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
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mov r4, #0x1 @ Number of parameters for restore call
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stmia r8!, {r4-r5} @ Push parameters for restore call
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mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
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stmia r8!, {r4-r5} @ Push parameters for restore call
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/* Check what that target sleep state is from r1 */
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cmp r1, #0x2 @ Only L2 lost, no need to save context
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beq clean_caches
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l1_logic_lost:
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/* Store sp and spsr to SDRAM */
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mov r4, sp
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mrs r5, spsr
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mov r6, lr
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stmia r8!, {r4-r6}
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/* Save all ARM registers */
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/* Coprocessor access control register */
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mrc p15, 0, r6, c1, c0, 2
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stmia r8!, {r6}
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/* TTBR0, TTBR1 and Translation table base control */
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mrc p15, 0, r4, c2, c0, 0
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mrc p15, 0, r5, c2, c0, 1
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mrc p15, 0, r6, c2, c0, 2
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stmia r8!, {r4-r6}
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/*
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* Domain access control register, data fault status register,
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* and instruction fault status register
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*/
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mrc p15, 0, r4, c3, c0, 0
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mrc p15, 0, r5, c5, c0, 0
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mrc p15, 0, r6, c5, c0, 1
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stmia r8!, {r4-r6}
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/*
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* Data aux fault status register, instruction aux fault status,
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* data fault address register and instruction fault address register
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*/
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mrc p15, 0, r4, c5, c1, 0
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mrc p15, 0, r5, c5, c1, 1
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mrc p15, 0, r6, c6, c0, 0
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mrc p15, 0, r7, c6, c0, 2
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stmia r8!, {r4-r7}
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/*
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* user r/w thread and process ID, user r/o thread and process ID,
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* priv only thread and process ID, cache size selection
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*/
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mrc p15, 0, r4, c13, c0, 2
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mrc p15, 0, r5, c13, c0, 3
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mrc p15, 0, r6, c13, c0, 4
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mrc p15, 2, r7, c0, c0, 0
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stmia r8!, {r4-r7}
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/* Data TLB lockdown, instruction TLB lockdown registers */
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mrc p15, 0, r5, c10, c0, 0
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mrc p15, 0, r6, c10, c0, 1
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stmia r8!, {r5-r6}
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/* Secure or non secure vector base address, FCSE PID, Context PID*/
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mrc p15, 0, r4, c12, c0, 0
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mrc p15, 0, r5, c13, c0, 0
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mrc p15, 0, r6, c13, c0, 1
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stmia r8!, {r4-r6}
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/* Primary remap, normal remap registers */
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mrc p15, 0, r4, c10, c2, 0
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mrc p15, 0, r5, c10, c2, 1
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stmia r8!,{r4-r5}
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/* Store current cpsr*/
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mrs r2, cpsr
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stmia r8!, {r2}
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mrc p15, 0, r4, c1, c0, 0
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/* save control register */
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stmia r8!, {r4}
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clean_caches:
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/*
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* jump out to kernel flush routine
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* - reuse that code is better
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* - it executes in a cached space so is faster than refetch per-block
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* - should be faster and will change with kernel
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* - 'might' have to copy address, load and jump to it
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*/
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ldr r1, kernel_flush
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blx r1
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/*
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* The kernel doesn't interwork: v7_flush_dcache_all in particluar will
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* always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
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* This sequence switches back to ARM. Note that .align may insert a
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* nop: bx pc needs to be word-aligned in order to work.
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*/
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THUMB( .thumb )
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THUMB( .align )
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THUMB( bx pc )
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THUMB( nop )
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.arm
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omap3_do_wfi:
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ldr r4, sdrc_power @ read the SDRC_POWER register
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ldr r5, [r4] @ read the contents of SDRC_POWER
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orr r5, r5, #0x40 @ enable self refresh on idle req
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str r5, [r4] @ write back to SDRC_POWER register
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/* Data memory barrier and Data sync barrier */
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dsb
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dmb
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/*
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* ===================================
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* == WFI instruction => Enter idle ==
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* ===================================
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*/
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wfi @ wait for interrupt
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/*
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* ===================================
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* == Resume path for non-OFF modes ==
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* ===================================
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*/
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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bl wait_sdrc_ok
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/*
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* ===================================
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* == Exit point from non-OFF modes ==
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* ===================================
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*/
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ldmfd sp!, {r0-r12, pc} @ restore regs and return
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/*
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* ==============================
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* == Resume path for OFF mode ==
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* ==============================
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*/
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/*
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* The restore_* functions are called by the ROM code
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* when back from WFI in OFF mode.
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* Cf. the get_*restore_pointer functions.
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*
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* restore_es3: applies to 34xx >= ES3.0
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* restore_3630: applies to 36xx
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* restore: common code for 3xxx
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*/
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restore_es3:
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ldr r5, pm_prepwstst_core_p
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ldr r4, [r5]
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and r4, r4, #0x3
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cmp r4, #0x0 @ Check if previous power state of CORE is OFF
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bne restore
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adr r0, es3_sdrc_fix
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ldr r1, sram_base
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ldr r2, es3_sdrc_fix_sz
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mov r2, r2, ror #2
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copy_to_sram:
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ldmia r0!, {r3} @ val = *src
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stmia r1!, {r3} @ *dst = val
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subs r2, r2, #0x1 @ num_words--
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bne copy_to_sram
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ldr r1, sram_base
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blx r1
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b restore
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restore_3630:
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ldr r1, pm_prepwstst_core_p
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ldr r2, [r1]
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and r2, r2, #0x3
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cmp r2, #0x0 @ Check if previous power state of CORE is OFF
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bne restore
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/* Disable RTA before giving control */
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ldr r1, control_mem_rta
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mov r2, #OMAP36XX_RTA_DISABLE
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str r2, [r1]
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/* Fall through to common code for the remaining logic */
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restore:
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/*
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* Check what was the reason for mpu reset and store the reason in r9:
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* 0 - No context lost
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* 1 - Only L1 and logic lost
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* 2 - Only L2 lost - In this case, we wont be here
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* 3 - Both L1 and L2 lost
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*/
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ldr r1, pm_pwstctrl_mpu
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ldr r2, [r1]
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and r2, r2, #0x3
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cmp r2, #0x0 @ Check if target power state was OFF or RET
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moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
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movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
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bne logic_l1_restore
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ldr r0, l2dis_3630
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cmp r0, #0x1 @ should we disable L2 on 3630?
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bne skipl2dis
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mrc p15, 0, r0, c1, c0, 1
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bic r0, r0, #2 @ disable L2 cache
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mcr p15, 0, r0, c1, c0, 1
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skipl2dis:
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ldr r0, control_stat
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ldr r1, [r0]
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and r1, #0x700
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cmp r1, #0x300
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beq l2_inv_gp
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mov r0, #40 @ set service ID for PPA
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mov r12, r0 @ copy secure Service ID in r12
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mov r1, #0 @ set task id for ROM code in r1
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mov r2, #4 @ set some flags in r2, r6
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mov r6, #0xff
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adr r3, l2_inv_api_params @ r3 points to dummy parameters
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dsb @ data write barrier
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dmb @ data memory barrier
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smc #1 @ call SMI monitor (smi #1)
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/* Write to Aux control register to set some bits */
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mov r0, #42 @ set service ID for PPA
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mov r12, r0 @ copy secure Service ID in r12
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mov r1, #0 @ set task id for ROM code in r1
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mov r2, #4 @ set some flags in r2, r6
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mov r6, #0xff
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ldr r4, scratchpad_base
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ldr r3, [r4, #0xBC] @ r3 points to parameters
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dsb @ data write barrier
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dmb @ data memory barrier
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smc #1 @ call SMI monitor (smi #1)
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#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
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/* Restore L2 aux control register */
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@ set service ID for PPA
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mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
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mov r12, r0 @ copy service ID in r12
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mov r1, #0 @ set task ID for ROM code in r1
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mov r2, #4 @ set some flags in r2, r6
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mov r6, #0xff
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ldr r4, scratchpad_base
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ldr r3, [r4, #0xBC]
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adds r3, r3, #8 @ r3 points to parameters
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dsb @ data write barrier
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dmb @ data memory barrier
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smc #1 @ call SMI monitor (smi #1)
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#endif
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b logic_l1_restore
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|
|
.align
|
|
l2_inv_api_params:
|
|
.word 0x1, 0x00
|
|
l2_inv_gp:
|
|
/* Execute smi to invalidate L2 cache */
|
|
mov r12, #0x1 @ set up to invalidate L2
|
|
smc #0 @ Call SMI monitor (smieq)
|
|
/* Write to Aux control register to set some bits */
|
|
ldr r4, scratchpad_base
|
|
ldr r3, [r4,#0xBC]
|
|
ldr r0, [r3,#4]
|
|
mov r12, #0x3
|
|
smc #0 @ Call SMI monitor (smieq)
|
|
ldr r4, scratchpad_base
|
|
ldr r3, [r4,#0xBC]
|
|
ldr r0, [r3,#12]
|
|
mov r12, #0x2
|
|
smc #0 @ Call SMI monitor (smieq)
|
|
logic_l1_restore:
|
|
ldr r1, l2dis_3630
|
|
cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
|
|
bne skipl2reen
|
|
mrc p15, 0, r1, c1, c0, 1
|
|
orr r1, r1, #2 @ re-enable L2 cache
|
|
mcr p15, 0, r1, c1, c0, 1
|
|
skipl2reen:
|
|
mov r1, #0
|
|
/*
|
|
* Invalidate all instruction caches to PoU
|
|
* and flush branch target cache
|
|
*/
|
|
mcr p15, 0, r1, c7, c5, 0
|
|
|
|
ldr r4, scratchpad_base
|
|
ldr r3, [r4,#0xBC]
|
|
adds r3, r3, #16
|
|
ldmia r3!, {r4-r6}
|
|
mov sp, r4
|
|
msr spsr_cxsf, r5
|
|
mov lr, r6
|
|
|
|
ldmia r3!, {r4-r9}
|
|
/* Coprocessor access Control Register */
|
|
mcr p15, 0, r4, c1, c0, 2
|
|
|
|
/* TTBR0 */
|
|
MCR p15, 0, r5, c2, c0, 0
|
|
/* TTBR1 */
|
|
MCR p15, 0, r6, c2, c0, 1
|
|
/* Translation table base control register */
|
|
MCR p15, 0, r7, c2, c0, 2
|
|
/* Domain access Control Register */
|
|
MCR p15, 0, r8, c3, c0, 0
|
|
/* Data fault status Register */
|
|
MCR p15, 0, r9, c5, c0, 0
|
|
|
|
ldmia r3!,{r4-r8}
|
|
/* Instruction fault status Register */
|
|
MCR p15, 0, r4, c5, c0, 1
|
|
/* Data Auxiliary Fault Status Register */
|
|
MCR p15, 0, r5, c5, c1, 0
|
|
/* Instruction Auxiliary Fault Status Register*/
|
|
MCR p15, 0, r6, c5, c1, 1
|
|
/* Data Fault Address Register */
|
|
MCR p15, 0, r7, c6, c0, 0
|
|
/* Instruction Fault Address Register*/
|
|
MCR p15, 0, r8, c6, c0, 2
|
|
ldmia r3!,{r4-r7}
|
|
|
|
/* User r/w thread and process ID */
|
|
MCR p15, 0, r4, c13, c0, 2
|
|
/* User ro thread and process ID */
|
|
MCR p15, 0, r5, c13, c0, 3
|
|
/* Privileged only thread and process ID */
|
|
MCR p15, 0, r6, c13, c0, 4
|
|
/* Cache size selection */
|
|
MCR p15, 2, r7, c0, c0, 0
|
|
ldmia r3!,{r4-r8}
|
|
/* Data TLB lockdown registers */
|
|
MCR p15, 0, r4, c10, c0, 0
|
|
/* Instruction TLB lockdown registers */
|
|
MCR p15, 0, r5, c10, c0, 1
|
|
/* Secure or Nonsecure Vector Base Address */
|
|
MCR p15, 0, r6, c12, c0, 0
|
|
/* FCSE PID */
|
|
MCR p15, 0, r7, c13, c0, 0
|
|
/* Context PID */
|
|
MCR p15, 0, r8, c13, c0, 1
|
|
|
|
ldmia r3!,{r4-r5}
|
|
/* Primary memory remap register */
|
|
MCR p15, 0, r4, c10, c2, 0
|
|
/* Normal memory remap register */
|
|
MCR p15, 0, r5, c10, c2, 1
|
|
|
|
/* Restore cpsr */
|
|
ldmia r3!,{r4} @ load CPSR from SDRAM
|
|
msr cpsr, r4 @ store cpsr
|
|
|
|
/* Enabling MMU here */
|
|
mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
|
|
/* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
|
|
and r7, #0x7
|
|
cmp r7, #0x0
|
|
beq usettbr0
|
|
ttbr_error:
|
|
/*
|
|
* More work needs to be done to support N[0:2] value other than 0
|
|
* So looping here so that the error can be detected
|
|
*/
|
|
b ttbr_error
|
|
usettbr0:
|
|
mrc p15, 0, r2, c2, c0, 0
|
|
ldr r5, ttbrbit_mask
|
|
and r2, r5
|
|
mov r4, pc
|
|
ldr r5, table_index_mask
|
|
and r4, r5 @ r4 = 31 to 20 bits of pc
|
|
/* Extract the value to be written to table entry */
|
|
ldr r1, table_entry
|
|
/* r1 has the value to be written to table entry*/
|
|
add r1, r1, r4
|
|
/* Getting the address of table entry to modify */
|
|
lsr r4, #18
|
|
/* r2 has the location which needs to be modified */
|
|
add r2, r4
|
|
/* Storing previous entry of location being modified */
|
|
ldr r5, scratchpad_base
|
|
ldr r4, [r2]
|
|
str r4, [r5, #0xC0]
|
|
/* Modify the table entry */
|
|
str r1, [r2]
|
|
/*
|
|
* Storing address of entry being modified
|
|
* - will be restored after enabling MMU
|
|
*/
|
|
ldr r5, scratchpad_base
|
|
str r2, [r5, #0xC4]
|
|
|
|
mov r0, #0
|
|
mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
|
|
mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
|
|
mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
|
|
mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
|
|
/*
|
|
* Restore control register. This enables the MMU.
|
|
* The caches and prediction are not enabled here, they
|
|
* will be enabled after restoring the MMU table entry.
|
|
*/
|
|
ldmia r3!, {r4}
|
|
/* Store previous value of control register in scratchpad */
|
|
str r4, [r5, #0xC8]
|
|
ldr r2, cache_pred_disable_mask
|
|
and r4, r2
|
|
mcr p15, 0, r4, c1, c0, 0
|
|
dsb
|
|
isb
|
|
ldr r0, =restoremmu_on
|
|
bx r0
|
|
|
|
/*
|
|
* ==============================
|
|
* == Exit point from OFF mode ==
|
|
* ==============================
|
|
*/
|
|
restoremmu_on:
|
|
ldmfd sp!, {r0-r12, pc} @ restore regs and return
|
|
|
|
|
|
/*
|
|
* Internal functions
|
|
*/
|
|
|
|
/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
|
|
.text
|
|
.align 3
|
|
ENTRY(es3_sdrc_fix)
|
|
ldr r4, sdrc_syscfg @ get config addr
|
|
ldr r5, [r4] @ get value
|
|
tst r5, #0x100 @ is part access blocked
|
|
it eq
|
|
biceq r5, r5, #0x100 @ clear bit if set
|
|
str r5, [r4] @ write back change
|
|
ldr r4, sdrc_mr_0 @ get config addr
|
|
ldr r5, [r4] @ get value
|
|
str r5, [r4] @ write back change
|
|
ldr r4, sdrc_emr2_0 @ get config addr
|
|
ldr r5, [r4] @ get value
|
|
str r5, [r4] @ write back change
|
|
ldr r4, sdrc_manual_0 @ get config addr
|
|
mov r5, #0x2 @ autorefresh command
|
|
str r5, [r4] @ kick off refreshes
|
|
ldr r4, sdrc_mr_1 @ get config addr
|
|
ldr r5, [r4] @ get value
|
|
str r5, [r4] @ write back change
|
|
ldr r4, sdrc_emr2_1 @ get config addr
|
|
ldr r5, [r4] @ get value
|
|
str r5, [r4] @ write back change
|
|
ldr r4, sdrc_manual_1 @ get config addr
|
|
mov r5, #0x2 @ autorefresh command
|
|
str r5, [r4] @ kick off refreshes
|
|
bx lr
|
|
|
|
.align
|
|
sdrc_syscfg:
|
|
.word SDRC_SYSCONFIG_P
|
|
sdrc_mr_0:
|
|
.word SDRC_MR_0_P
|
|
sdrc_emr2_0:
|
|
.word SDRC_EMR2_0_P
|
|
sdrc_manual_0:
|
|
.word SDRC_MANUAL_0_P
|
|
sdrc_mr_1:
|
|
.word SDRC_MR_1_P
|
|
sdrc_emr2_1:
|
|
.word SDRC_EMR2_1_P
|
|
sdrc_manual_1:
|
|
.word SDRC_MANUAL_1_P
|
|
ENDPROC(es3_sdrc_fix)
|
|
ENTRY(es3_sdrc_fix_sz)
|
|
.word . - es3_sdrc_fix
|
|
|
|
/*
|
|
* This function implements the erratum ID i581 WA:
|
|
* SDRC state restore before accessing the SDRAM
|
|
*
|
|
* Only used at return from non-OFF mode. For OFF
|
|
* mode the ROM code configures the SDRC and
|
|
* the DPLL before calling the restore code directly
|
|
* from DDR.
|
|
*/
|
|
|
|
/* Make sure SDRC accesses are ok */
|
|
wait_sdrc_ok:
|
|
|
|
/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
|
|
ldr r4, cm_idlest_ckgen
|
|
wait_dpll3_lock:
|
|
ldr r5, [r4]
|
|
tst r5, #1
|
|
beq wait_dpll3_lock
|
|
|
|
ldr r4, cm_idlest1_core
|
|
wait_sdrc_ready:
|
|
ldr r5, [r4]
|
|
tst r5, #0x2
|
|
bne wait_sdrc_ready
|
|
/* allow DLL powerdown upon hw idle req */
|
|
ldr r4, sdrc_power
|
|
ldr r5, [r4]
|
|
bic r5, r5, #0x40
|
|
str r5, [r4]
|
|
|
|
/*
|
|
* PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a
|
|
* base instead.
|
|
* Be careful not to clobber r7 when maintaing this code.
|
|
*/
|
|
|
|
is_dll_in_lock_mode:
|
|
/* Is dll in lock mode? */
|
|
ldr r4, sdrc_dlla_ctrl
|
|
ldr r5, [r4]
|
|
tst r5, #0x4
|
|
bxne lr @ Return if locked
|
|
/* wait till dll locks */
|
|
adr r7, kick_counter
|
|
wait_dll_lock_timed:
|
|
ldr r4, wait_dll_lock_counter
|
|
add r4, r4, #1
|
|
str r4, [r7, #wait_dll_lock_counter - kick_counter]
|
|
ldr r4, sdrc_dlla_status
|
|
/* Wait 20uS for lock */
|
|
mov r6, #8
|
|
wait_dll_lock:
|
|
subs r6, r6, #0x1
|
|
beq kick_dll
|
|
ldr r5, [r4]
|
|
and r5, r5, #0x4
|
|
cmp r5, #0x4
|
|
bne wait_dll_lock
|
|
bx lr @ Return when locked
|
|
|
|
/* disable/reenable DLL if not locked */
|
|
kick_dll:
|
|
ldr r4, sdrc_dlla_ctrl
|
|
ldr r5, [r4]
|
|
mov r6, r5
|
|
bic r6, #(1<<3) @ disable dll
|
|
str r6, [r4]
|
|
dsb
|
|
orr r6, r6, #(1<<3) @ enable dll
|
|
str r6, [r4]
|
|
dsb
|
|
ldr r4, kick_counter
|
|
add r4, r4, #1
|
|
str r4, [r7] @ kick_counter
|
|
b wait_dll_lock_timed
|
|
|
|
.align
|
|
cm_idlest1_core:
|
|
.word CM_IDLEST1_CORE_V
|
|
cm_idlest_ckgen:
|
|
.word CM_IDLEST_CKGEN_V
|
|
sdrc_dlla_status:
|
|
.word SDRC_DLLA_STATUS_V
|
|
sdrc_dlla_ctrl:
|
|
.word SDRC_DLLA_CTRL_V
|
|
pm_prepwstst_core_p:
|
|
.word PM_PREPWSTST_CORE_P
|
|
pm_pwstctrl_mpu:
|
|
.word PM_PWSTCTRL_MPU_P
|
|
scratchpad_base:
|
|
.word SCRATCHPAD_BASE_P
|
|
sram_base:
|
|
.word SRAM_BASE_P + 0x8000
|
|
sdrc_power:
|
|
.word SDRC_POWER_V
|
|
ttbrbit_mask:
|
|
.word 0xFFFFC000
|
|
table_index_mask:
|
|
.word 0xFFF00000
|
|
table_entry:
|
|
.word 0x00000C02
|
|
cache_pred_disable_mask:
|
|
.word 0xFFFFE7FB
|
|
control_stat:
|
|
.word CONTROL_STAT
|
|
control_mem_rta:
|
|
.word CONTROL_MEM_RTA_CTRL
|
|
kernel_flush:
|
|
.word v7_flush_dcache_all
|
|
l2dis_3630:
|
|
.word 0
|
|
/*
|
|
* When exporting to userspace while the counters are in SRAM,
|
|
* these 2 words need to be at the end to facilitate retrival!
|
|
*/
|
|
kick_counter:
|
|
.word 0
|
|
wait_dll_lock_counter:
|
|
.word 0
|
|
ENDPROC(omap34xx_cpu_suspend)
|
|
|
|
ENTRY(omap34xx_cpu_suspend_sz)
|
|
.word . - omap34xx_cpu_suspend
|