c902be71dc
This patch enables support for pause(0) power management state for the Cell Broadband Processor, which is import for power efficient operation. The pervasive infrastructure will in the future enable us to introduce more functionality specific to the Cell's pervasive unit. From: Maximino Aguilar <maguilar@us.ibm.com> Signed-off-by: Arnd Bergmann <arndb@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
636 lines
15 KiB
C
636 lines
15 KiB
C
/*
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* 64-bit pSeries and RS/6000 setup code.
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*
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* Copyright (C) 1995 Linus Torvalds
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* Adapted from 'alpha' version by Gary Thomas
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* Modified by PPC64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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/*
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* bootup setup stuff..
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*/
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#undef DEBUG
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#include <linux/config.h>
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#include <linux/cpu.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/slab.h>
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#include <linux/user.h>
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#include <linux/a.out.h>
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#include <linux/tty.h>
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#include <linux/major.h>
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#include <linux/interrupt.h>
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#include <linux/reboot.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/console.h>
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#include <linux/pci.h>
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#include <linux/utsname.h>
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#include <linux/adb.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/prom.h>
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#include <asm/rtas.h>
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#include <asm/pci-bridge.h>
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#include <asm/iommu.h>
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#include <asm/dma.h>
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#include <asm/machdep.h>
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#include <asm/irq.h>
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#include <asm/kexec.h>
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#include <asm/time.h>
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#include <asm/nvram.h>
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#include "xics.h"
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#include <asm/firmware.h>
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#include <asm/pmc.h>
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#include <asm/mpic.h>
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#include <asm/ppc-pci.h>
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#include <asm/i8259.h>
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#include <asm/udbg.h>
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#include <asm/smp.h>
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#include "plpar_wrappers.h"
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#include "ras.h"
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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extern void find_udbg_vterm(void);
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int fwnmi_active; /* TRUE if an FWNMI handler is present */
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static void pseries_shared_idle(void);
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static void pseries_dedicated_idle(void);
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struct mpic *pSeries_mpic;
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void pSeries_show_cpuinfo(struct seq_file *m)
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{
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struct device_node *root;
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const char *model = "";
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root = of_find_node_by_path("/");
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if (root)
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model = get_property(root, "model", NULL);
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seq_printf(m, "machine\t\t: CHRP %s\n", model);
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of_node_put(root);
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}
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/* Initialize firmware assisted non-maskable interrupts if
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* the firmware supports this feature.
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*/
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static void __init fwnmi_init(void)
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{
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unsigned long system_reset_addr, machine_check_addr;
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int ibm_nmi_register = rtas_token("ibm,nmi-register");
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if (ibm_nmi_register == RTAS_UNKNOWN_SERVICE)
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return;
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/* If the kernel's not linked at zero we point the firmware at low
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* addresses anyway, and use a trampoline to get to the real code. */
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system_reset_addr = __pa(system_reset_fwnmi) - PHYSICAL_START;
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machine_check_addr = __pa(machine_check_fwnmi) - PHYSICAL_START;
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if (0 == rtas_call(ibm_nmi_register, 2, 1, NULL, system_reset_addr,
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machine_check_addr))
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fwnmi_active = 1;
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}
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static void __init pSeries_init_mpic(void)
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{
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unsigned int *addrp;
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struct device_node *np;
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unsigned long intack = 0;
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/* All ISUs are setup, complete initialization */
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mpic_init(pSeries_mpic);
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/* Check what kind of cascade ACK we have */
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if (!(np = of_find_node_by_name(NULL, "pci"))
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|| !(addrp = (unsigned int *)
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get_property(np, "8259-interrupt-acknowledge", NULL)))
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printk(KERN_ERR "Cannot find pci to get ack address\n");
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else
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intack = addrp[prom_n_addr_cells(np)-1];
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of_node_put(np);
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/* Setup the legacy interrupts & controller */
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i8259_init(intack, 0);
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/* Hook cascade to mpic */
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mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
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}
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static void __init pSeries_setup_mpic(void)
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{
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unsigned int *opprop;
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unsigned long openpic_addr = 0;
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unsigned char senses[NR_IRQS - NUM_ISA_INTERRUPTS];
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struct device_node *root;
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int irq_count;
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/* Find the Open PIC if present */
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root = of_find_node_by_path("/");
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opprop = (unsigned int *) get_property(root, "platform-open-pic", NULL);
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if (opprop != 0) {
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int n = prom_n_addr_cells(root);
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for (openpic_addr = 0; n > 0; --n)
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openpic_addr = (openpic_addr << 32) + *opprop++;
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printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
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}
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of_node_put(root);
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BUG_ON(openpic_addr == 0);
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/* Get the sense values from OF */
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prom_get_irq_senses(senses, NUM_ISA_INTERRUPTS, NR_IRQS);
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/* Setup the openpic driver */
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irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
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pSeries_mpic = mpic_alloc(openpic_addr, MPIC_PRIMARY,
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16, 16, irq_count, /* isu size, irq offset, irq count */
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NR_IRQS - 4, /* ipi offset */
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senses, irq_count, /* sense & sense size */
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" MPIC ");
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}
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static void pseries_lpar_enable_pmcs(void)
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{
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unsigned long set, reset;
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power4_enable_pmcs();
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set = 1UL << 63;
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reset = 0;
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plpar_hcall_norets(H_PERFMON, set, reset);
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/* instruct hypervisor to maintain PMCs */
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if (firmware_has_feature(FW_FEATURE_SPLPAR))
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get_paca()->lppaca.pmcregs_in_use = 1;
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}
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static void __init pSeries_setup_arch(void)
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{
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/* Fixup ppc_md depending on the type of interrupt controller */
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if (ppc64_interrupt_controller == IC_OPEN_PIC) {
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ppc_md.init_IRQ = pSeries_init_mpic;
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ppc_md.get_irq = mpic_get_irq;
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/* Allocate the mpic now, so that find_and_init_phbs() can
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* fill the ISUs */
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pSeries_setup_mpic();
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} else {
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ppc_md.init_IRQ = xics_init_IRQ;
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ppc_md.get_irq = xics_get_irq;
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}
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#ifdef CONFIG_SMP
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smp_init_pSeries();
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#endif
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/* openpic global configuration register (64-bit format). */
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/* openpic Interrupt Source Unit pointer (64-bit format). */
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/* python0 facility area (mmio) (64-bit format) REAL address. */
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000;
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if (ROOT_DEV == 0) {
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printk("No ramdisk, default root is /dev/sda2\n");
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ROOT_DEV = Root_SDA2;
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}
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fwnmi_init();
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/* Find and initialize PCI host bridges */
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init_pci_config_tokens();
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find_and_init_phbs();
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eeh_init();
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pSeries_nvram_init();
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/* Choose an idle loop */
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if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
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vpa_init(boot_cpuid);
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if (get_paca()->lppaca.shared_proc) {
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printk(KERN_INFO "Using shared processor idle loop\n");
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ppc_md.idle_loop = pseries_shared_idle;
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} else {
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printk(KERN_INFO "Using dedicated idle loop\n");
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ppc_md.idle_loop = pseries_dedicated_idle;
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}
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} else {
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printk(KERN_INFO "Using default idle loop\n");
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ppc_md.idle_loop = default_idle;
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}
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if (platform_is_lpar())
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ppc_md.enable_pmcs = pseries_lpar_enable_pmcs;
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else
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ppc_md.enable_pmcs = power4_enable_pmcs;
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}
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static int __init pSeries_init_panel(void)
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{
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/* Manually leave the kernel version on the panel. */
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ppc_md.progress("Linux ppc64\n", 0);
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ppc_md.progress(system_utsname.version, 0);
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return 0;
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}
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arch_initcall(pSeries_init_panel);
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/* Build up the ppc64_firmware_features bitmask field
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* using contents of device-tree/ibm,hypertas-functions.
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* Ultimately this functionality may be moved into prom.c prom_init().
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*/
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static void __init fw_feature_init(void)
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{
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struct device_node * dn;
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char * hypertas;
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unsigned int len;
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DBG(" -> fw_feature_init()\n");
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ppc64_firmware_features = 0;
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dn = of_find_node_by_path("/rtas");
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if (dn == NULL) {
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printk(KERN_ERR "WARNING ! Cannot find RTAS in device-tree !\n");
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goto no_rtas;
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}
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hypertas = get_property(dn, "ibm,hypertas-functions", &len);
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if (hypertas) {
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while (len > 0){
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int i, hypertas_len;
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/* check value against table of strings */
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for(i=0; i < FIRMWARE_MAX_FEATURES ;i++) {
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if ((firmware_features_table[i].name) &&
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(strcmp(firmware_features_table[i].name,hypertas))==0) {
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/* we have a match */
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ppc64_firmware_features |=
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(firmware_features_table[i].val);
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break;
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}
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}
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hypertas_len = strlen(hypertas);
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len -= hypertas_len +1;
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hypertas+= hypertas_len +1;
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}
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}
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of_node_put(dn);
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no_rtas:
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DBG(" <- fw_feature_init()\n");
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}
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static void __init pSeries_discover_pic(void)
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{
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struct device_node *np;
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char *typep;
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/*
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* Setup interrupt mapping options that are needed for finish_device_tree
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* to properly parse the OF interrupt tree & do the virtual irq mapping
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*/
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__irq_offset_value = NUM_ISA_INTERRUPTS;
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ppc64_interrupt_controller = IC_INVALID;
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for (np = NULL; (np = of_find_node_by_name(np, "interrupt-controller"));) {
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typep = (char *)get_property(np, "compatible", NULL);
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if (strstr(typep, "open-pic")) {
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ppc64_interrupt_controller = IC_OPEN_PIC;
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break;
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} else if (strstr(typep, "ppc-xicp")) {
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ppc64_interrupt_controller = IC_PPC_XIC;
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break;
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}
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}
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if (ppc64_interrupt_controller == IC_INVALID)
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printk("pSeries_discover_pic: failed to recognize"
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" interrupt-controller\n");
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}
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static void pSeries_mach_cpu_die(void)
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{
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local_irq_disable();
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idle_task_exit();
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/* Some hardware requires clearing the CPPR, while other hardware does not
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* it is safe either way
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*/
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pSeriesLP_cppr_info(0, 0);
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rtas_stop_self();
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/* Should never get here... */
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BUG();
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for(;;);
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}
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static int pseries_set_dabr(unsigned long dabr)
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{
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return plpar_hcall_norets(H_SET_DABR, dabr);
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}
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static int pseries_set_xdabr(unsigned long dabr)
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{
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/* We want to catch accesses from kernel and userspace */
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return plpar_hcall_norets(H_SET_XDABR, dabr,
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H_DABRX_KERNEL | H_DABRX_USER);
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}
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/*
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* Early initialization. Relocation is on but do not reference unbolted pages
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*/
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static void __init pSeries_init_early(void)
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{
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int iommu_off = 0;
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DBG(" -> pSeries_init_early()\n");
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fw_feature_init();
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if (platform_is_lpar())
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hpte_init_lpar();
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else {
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hpte_init_native();
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iommu_off = (of_chosen &&
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get_property(of_chosen, "linux,iommu-off", NULL));
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}
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if (platform_is_lpar())
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find_udbg_vterm();
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if (firmware_has_feature(FW_FEATURE_DABR))
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ppc_md.set_dabr = pseries_set_dabr;
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else if (firmware_has_feature(FW_FEATURE_XDABR))
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ppc_md.set_dabr = pseries_set_xdabr;
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iommu_init_early_pSeries();
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pSeries_discover_pic();
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DBG(" <- pSeries_init_early()\n");
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}
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static int pSeries_check_legacy_ioport(unsigned int baseport)
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{
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struct device_node *np;
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#define I8042_DATA_REG 0x60
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#define FDC_BASE 0x3f0
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switch(baseport) {
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case I8042_DATA_REG:
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np = of_find_node_by_type(NULL, "8042");
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if (np == NULL)
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return -ENODEV;
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of_node_put(np);
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break;
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case FDC_BASE:
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np = of_find_node_by_type(NULL, "fdc");
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if (np == NULL)
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return -ENODEV;
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of_node_put(np);
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break;
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}
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return 0;
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}
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/*
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* Called very early, MMU is off, device-tree isn't unflattened
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*/
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extern struct machdep_calls pSeries_md;
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static int __init pSeries_probe(int platform)
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{
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if (platform != PLATFORM_PSERIES &&
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platform != PLATFORM_PSERIES_LPAR)
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return 0;
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/* if we have some ppc_md fixups for LPAR to do, do
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* it here ...
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*/
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return 1;
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}
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DECLARE_PER_CPU(unsigned long, smt_snooze_delay);
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static inline void dedicated_idle_sleep(unsigned int cpu)
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{
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struct paca_struct *ppaca = &paca[cpu ^ 1];
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/* Only sleep if the other thread is not idle */
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if (!(ppaca->lppaca.idle)) {
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local_irq_disable();
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/*
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* We are about to sleep the thread and so wont be polling any
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* more.
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*/
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clear_thread_flag(TIF_POLLING_NRFLAG);
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smp_mb__after_clear_bit();
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/*
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* SMT dynamic mode. Cede will result in this thread going
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* dormant, if the partner thread is still doing work. Thread
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* wakes up if partner goes idle, an interrupt is presented, or
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* a prod occurs. Returning from the cede enables external
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* interrupts.
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*/
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if (!need_resched())
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cede_processor();
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else
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local_irq_enable();
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set_thread_flag(TIF_POLLING_NRFLAG);
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} else {
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/*
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* Give the HV an opportunity at the processor, since we are
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* not doing any work.
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*/
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poll_pending();
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}
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}
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static void pseries_dedicated_idle(void)
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{
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struct paca_struct *lpaca = get_paca();
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unsigned int cpu = smp_processor_id();
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unsigned long start_snooze;
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unsigned long *smt_snooze_delay = &__get_cpu_var(smt_snooze_delay);
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set_thread_flag(TIF_POLLING_NRFLAG);
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while (1) {
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/*
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* Indicate to the HV that we are idle. Now would be
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* a good time to find other work to dispatch.
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*/
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lpaca->lppaca.idle = 1;
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if (!need_resched()) {
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start_snooze = get_tb() +
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*smt_snooze_delay * tb_ticks_per_usec;
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while (!need_resched() && !cpu_is_offline(cpu)) {
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ppc64_runlatch_off();
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/*
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* Go into low thread priority and possibly
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* low power mode.
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*/
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HMT_low();
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HMT_very_low();
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if (*smt_snooze_delay != 0 &&
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get_tb() > start_snooze) {
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HMT_medium();
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dedicated_idle_sleep(cpu);
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}
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}
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HMT_medium();
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}
|
|
|
|
lpaca->lppaca.idle = 0;
|
|
ppc64_runlatch_on();
|
|
|
|
preempt_enable_no_resched();
|
|
schedule();
|
|
preempt_disable();
|
|
|
|
if (cpu_is_offline(cpu) && system_state == SYSTEM_RUNNING)
|
|
cpu_die();
|
|
}
|
|
}
|
|
|
|
static void pseries_shared_idle(void)
|
|
{
|
|
struct paca_struct *lpaca = get_paca();
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
while (1) {
|
|
/*
|
|
* Indicate to the HV that we are idle. Now would be
|
|
* a good time to find other work to dispatch.
|
|
*/
|
|
lpaca->lppaca.idle = 1;
|
|
|
|
while (!need_resched() && !cpu_is_offline(cpu)) {
|
|
local_irq_disable();
|
|
ppc64_runlatch_off();
|
|
|
|
/*
|
|
* Yield the processor to the hypervisor. We return if
|
|
* an external interrupt occurs (which are driven prior
|
|
* to returning here) or if a prod occurs from another
|
|
* processor. When returning here, external interrupts
|
|
* are enabled.
|
|
*
|
|
* Check need_resched() again with interrupts disabled
|
|
* to avoid a race.
|
|
*/
|
|
if (!need_resched())
|
|
cede_processor();
|
|
else
|
|
local_irq_enable();
|
|
|
|
HMT_medium();
|
|
}
|
|
|
|
lpaca->lppaca.idle = 0;
|
|
ppc64_runlatch_on();
|
|
|
|
preempt_enable_no_resched();
|
|
schedule();
|
|
preempt_disable();
|
|
|
|
if (cpu_is_offline(cpu) && system_state == SYSTEM_RUNNING)
|
|
cpu_die();
|
|
}
|
|
}
|
|
|
|
static int pSeries_pci_probe_mode(struct pci_bus *bus)
|
|
{
|
|
if (platform_is_lpar())
|
|
return PCI_PROBE_DEVTREE;
|
|
return PCI_PROBE_NORMAL;
|
|
}
|
|
|
|
#ifdef CONFIG_KEXEC
|
|
static void pseries_kexec_cpu_down(int crash_shutdown, int secondary)
|
|
{
|
|
/* Don't risk a hypervisor call if we're crashing */
|
|
if (!crash_shutdown) {
|
|
unsigned long vpa = __pa(&get_paca()->lppaca);
|
|
|
|
if (unregister_vpa(hard_smp_processor_id(), vpa)) {
|
|
printk("VPA deregistration of cpu %u (hw_cpu_id %d) "
|
|
"failed\n", smp_processor_id(),
|
|
hard_smp_processor_id());
|
|
}
|
|
}
|
|
|
|
if (ppc64_interrupt_controller == IC_OPEN_PIC)
|
|
mpic_teardown_this_cpu(secondary);
|
|
else
|
|
xics_teardown_cpu(secondary);
|
|
}
|
|
#endif
|
|
|
|
struct machdep_calls __initdata pSeries_md = {
|
|
.probe = pSeries_probe,
|
|
.setup_arch = pSeries_setup_arch,
|
|
.init_early = pSeries_init_early,
|
|
.show_cpuinfo = pSeries_show_cpuinfo,
|
|
.log_error = pSeries_log_error,
|
|
.pcibios_fixup = pSeries_final_fixup,
|
|
.pci_probe_mode = pSeries_pci_probe_mode,
|
|
.irq_bus_setup = pSeries_irq_bus_setup,
|
|
.restart = rtas_restart,
|
|
.power_off = rtas_power_off,
|
|
.halt = rtas_halt,
|
|
.panic = rtas_os_term,
|
|
.cpu_die = pSeries_mach_cpu_die,
|
|
.get_boot_time = rtas_get_boot_time,
|
|
.get_rtc_time = rtas_get_rtc_time,
|
|
.set_rtc_time = rtas_set_rtc_time,
|
|
.calibrate_decr = generic_calibrate_decr,
|
|
.progress = rtas_progress,
|
|
.check_legacy_ioport = pSeries_check_legacy_ioport,
|
|
.system_reset_exception = pSeries_system_reset_exception,
|
|
.machine_check_exception = pSeries_machine_check_exception,
|
|
#ifdef CONFIG_KEXEC
|
|
.kexec_cpu_down = pseries_kexec_cpu_down,
|
|
.machine_kexec = default_machine_kexec,
|
|
.machine_kexec_prepare = default_machine_kexec_prepare,
|
|
.machine_crash_shutdown = default_machine_crash_shutdown,
|
|
#endif
|
|
};
|