c59c464a3e
On ppc64 machines with segment tables, CPU0's segment table is at a fixed address, currently 0x9000. This patch moves it to the free space at 0x6000, just below the fwnmi data area. This saves 8k of space in vmlinux and the runtime kernel image. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
351 lines
10 KiB
C
351 lines
10 KiB
C
/*
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* PowerPC memory management structures
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*
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* Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
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* PPC64 rework.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _PPC64_MMU_H_
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#define _PPC64_MMU_H_
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#include <linux/config.h>
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#include <asm/page.h>
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/*
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* Segment table
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*/
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#define STE_ESID_V 0x80
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#define STE_ESID_KS 0x20
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#define STE_ESID_KP 0x10
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#define STE_ESID_N 0x08
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#define STE_VSID_SHIFT 12
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/* Location of cpu0's segment table */
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#define STAB0_PAGE 0x6
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#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
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#ifndef __ASSEMBLY__
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extern char initial_stab[];
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#endif /* ! __ASSEMBLY */
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/*
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* SLB
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*/
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#define SLB_NUM_BOLTED 3
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#define SLB_CACHE_ENTRIES 8
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/* Bits in the SLB ESID word */
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#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
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/* Bits in the SLB VSID word */
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#define SLB_VSID_SHIFT 12
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#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
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#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
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#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
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#define SLB_VSID_L ASM_CONST(0x0000000000000100) /* largepage */
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#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
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#define SLB_VSID_LS ASM_CONST(0x0000000000000070) /* size of largepage */
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#define SLB_VSID_KERNEL (SLB_VSID_KP|SLB_VSID_C)
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#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS)
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/*
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* Hash table
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*/
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#define HPTES_PER_GROUP 8
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#define HPTE_V_AVPN_SHIFT 7
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#define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80)
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
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#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
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#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
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#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
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#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
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#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
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#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
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#define HPTE_R_TS ASM_CONST(0x4000000000000000)
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#define HPTE_R_RPN_SHIFT 12
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#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
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#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
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#define HPTE_R_PP ASM_CONST(0x0000000000000003)
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/* Values for PP (assumes Ks=0, Kp=1) */
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/* pp0 will always be 0 for linux */
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#define PP_RWXX 0 /* Supervisor read/write, User none */
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#define PP_RWRX 1 /* Supervisor read/write, User read */
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#define PP_RWRW 2 /* Supervisor read/write, User read/write */
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#define PP_RXRX 3 /* Supervisor read, User read */
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#ifndef __ASSEMBLY__
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typedef struct {
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unsigned long v;
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unsigned long r;
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} hpte_t;
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extern hpte_t *htab_address;
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extern unsigned long htab_hash_mask;
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static inline unsigned long hpt_hash(unsigned long vpn, int large)
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{
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unsigned long vsid;
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unsigned long page;
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if (large) {
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vsid = vpn >> 4;
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page = vpn & 0xf;
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} else {
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vsid = vpn >> 16;
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page = vpn & 0xffff;
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}
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return (vsid & 0x7fffffffffUL) ^ page;
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}
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static inline void __tlbie(unsigned long va, int large)
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{
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/* clear top 16 bits, non SLS segment */
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va &= ~(0xffffULL << 48);
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if (large) {
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va &= HPAGE_MASK;
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asm volatile("tlbie %0,1" : : "r"(va) : "memory");
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} else {
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va &= PAGE_MASK;
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asm volatile("tlbie %0,0" : : "r"(va) : "memory");
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}
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}
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static inline void tlbie(unsigned long va, int large)
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{
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asm volatile("ptesync": : :"memory");
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__tlbie(va, large);
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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static inline void __tlbiel(unsigned long va)
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{
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/* clear top 16 bits, non SLS segment */
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va &= ~(0xffffULL << 48);
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va &= PAGE_MASK;
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/*
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* Thanks to Alan Modra we are now able to use machine specific
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* assembly instructions (like tlbiel) by using the gas -many flag.
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* However we have to support older toolchains so for the moment
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* we hardwire it.
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*/
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#if 0
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asm volatile("tlbiel %0" : : "r"(va) : "memory");
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#else
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asm volatile(".long 0x7c000224 | (%0 << 11)" : : "r"(va) : "memory");
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#endif
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}
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static inline void tlbiel(unsigned long va)
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{
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asm volatile("ptesync": : :"memory");
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__tlbiel(va);
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asm volatile("ptesync": : :"memory");
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}
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static inline unsigned long slot2va(unsigned long hpte_v, unsigned long slot)
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{
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unsigned long avpn = HPTE_V_AVPN_VAL(hpte_v);
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unsigned long va;
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va = avpn << 23;
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if (! (hpte_v & HPTE_V_LARGE)) {
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unsigned long vpi, pteg;
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pteg = slot / HPTES_PER_GROUP;
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if (hpte_v & HPTE_V_SECONDARY)
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pteg = ~pteg;
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vpi = ((va >> 28) ^ pteg) & htab_hash_mask;
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va |= vpi << PAGE_SHIFT;
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}
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return va;
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}
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/*
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* Handle a fault by adding an HPTE. If the address can't be determined
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* to be valid via Linux page tables, return 1. If handled return 0
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*/
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extern int __hash_page(unsigned long ea, unsigned long access,
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unsigned long vsid, pte_t *ptep, unsigned long trap,
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int local);
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extern void htab_finish_init(void);
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extern void hpte_init_native(void);
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extern void hpte_init_lpar(void);
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extern void hpte_init_iSeries(void);
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extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
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unsigned long va, unsigned long prpn,
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unsigned long vflags,
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unsigned long rflags);
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extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
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unsigned long prpn,
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unsigned long vflags, unsigned long rflags);
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extern void stabs_alloc(void);
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#endif /* __ASSEMBLY__ */
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/*
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* VSID allocation
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*
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* We first generate a 36-bit "proto-VSID". For kernel addresses this
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* is equal to the ESID, for user addresses it is:
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* (context << 15) | (esid & 0x7fff)
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*
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* The two forms are distinguishable because the top bit is 0 for user
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* addresses, whereas the top two bits are 1 for kernel addresses.
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* Proto-VSIDs with the top two bits equal to 0b10 are reserved for
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* now.
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*
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* The proto-VSIDs are then scrambled into real VSIDs with the
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* multiplicative hash:
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*
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* VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
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* where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
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* VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
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*
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* This scramble is only well defined for proto-VSIDs below
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* 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
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* reserved. VSID_MULTIPLIER is prime, so in particular it is
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* co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
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* Because the modulus is 2^n-1 we can compute it efficiently without
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* a divide or extra multiply (see below).
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*
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* This scheme has several advantages over older methods:
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*
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* - We have VSIDs allocated for every kernel address
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* (i.e. everything above 0xC000000000000000), except the very top
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* segment, which simplifies several things.
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*
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* - We allow for 15 significant bits of ESID and 20 bits of
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* context for user addresses. i.e. 8T (43 bits) of address space for
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* up to 1M contexts (although the page table structure and context
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* allocation will need changes to take advantage of this).
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*
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* - The scramble function gives robust scattering in the hash
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* table (at least based on some initial results). The previous
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* method was more susceptible to pathological cases giving excessive
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* hash collisions.
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*/
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/*
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* WARNING - If you change these you must make sure the asm
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* implementations in slb_allocate (slb_low.S), do_stab_bolted
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* (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
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*
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* You'll also need to change the precomputed VSID values in head.S
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* which are used by the iSeries firmware.
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*/
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#define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */
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#define VSID_BITS 36
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#define VSID_MODULUS ((1UL<<VSID_BITS)-1)
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#define CONTEXT_BITS 19
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#define USER_ESID_BITS 16
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#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
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/*
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* This macro generates asm code to compute the VSID scramble
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* function. Used in slb_allocate() and do_stab_bolted. The function
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* computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
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*
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* rt = register continaing the proto-VSID and into which the
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* VSID will be stored
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* rx = scratch register (clobbered)
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*
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* - rt and rx must be different registers
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* - The answer will end up in the low 36 bits of rt. The higher
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* bits may contain other garbage, so you may need to mask the
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* result.
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*/
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#define ASM_VSID_SCRAMBLE(rt, rx) \
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lis rx,VSID_MULTIPLIER@h; \
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ori rx,rx,VSID_MULTIPLIER@l; \
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mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
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\
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srdi rx,rt,VSID_BITS; \
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clrldi rt,rt,(64-VSID_BITS); \
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add rt,rt,rx; /* add high and low bits */ \
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/* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
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* 2^36-1+2^28-1. That in particular means that if r3 >= \
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* 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
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* the bit clear, r3 already has the answer we want, if it \
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* doesn't, the answer is the low 36 bits of r3+1. So in all \
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* cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
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addi rx,rt,1; \
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srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \
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add rt,rt,rx
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#ifndef __ASSEMBLY__
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typedef unsigned long mm_context_id_t;
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typedef struct {
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mm_context_id_t id;
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#ifdef CONFIG_HUGETLB_PAGE
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u16 htlb_segs; /* bitmask */
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#endif
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} mm_context_t;
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static inline unsigned long vsid_scramble(unsigned long protovsid)
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{
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#if 0
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/* The code below is equivalent to this function for arguments
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* < 2^VSID_BITS, which is all this should ever be called
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* with. However gcc is not clever enough to compute the
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* modulus (2^n-1) without a second multiply. */
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return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
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#else /* 1 */
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unsigned long x;
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x = protovsid * VSID_MULTIPLIER;
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x = (x >> VSID_BITS) + (x & VSID_MODULUS);
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return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
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#endif /* 1 */
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}
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/* This is only valid for addresses >= KERNELBASE */
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static inline unsigned long get_kernel_vsid(unsigned long ea)
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{
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return vsid_scramble(ea >> SID_SHIFT);
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}
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/* This is only valid for user addresses (which are below 2^41) */
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static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
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{
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return vsid_scramble((context << USER_ESID_BITS)
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| (ea >> SID_SHIFT));
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}
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#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
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#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
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#endif /* __ASSEMBLY */
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#endif /* _PPC64_MMU_H_ */
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