8726e4f50e
The "legacy irq controller" duplicates the functionality of the GIC, but remains powered during the cpu suspend and idle modes that power down the CPU and the GIC. Signed-off-by: Colin Cross <ccross@android.com>
115 lines
2.8 KiB
C
115 lines
2.8 KiB
C
/*
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* arch/arm/mach-tegra/legacy_irq.c
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*
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* Copyright (C) 2010 Google, Inc.
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* Author: Colin Cross <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <mach/iomap.h>
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#include <mach/legacy_irq.h>
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#define ICTLR_CPU_IER 0x20
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#define ICTLR_CPU_IER_SET 0x24
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#define ICTLR_CPU_IER_CLR 0x28
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#define ICTLR_CPU_IEP_CLASS 0x2C
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#define ICTLR_CPU_IEP_VFIQ 0x08
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#define ICTLR_CPU_IEP_FIR 0x14
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#define ICTLR_CPU_IEP_FIR_SET 0x18
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#define ICTLR_CPU_IEP_FIR_CLR 0x1c
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static void __iomem *ictlr_reg_base[] = {
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IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
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IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
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IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
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IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
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};
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/* When going into deep sleep, the CPU is powered down, taking the GIC with it
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In order to wake, the wake interrupts need to be enabled in the legacy
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interrupt controller. */
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void tegra_legacy_unmask_irq(unsigned int irq)
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{
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void __iomem *base;
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pr_debug("%s: %d\n", __func__, irq);
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irq -= 32;
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base = ictlr_reg_base[irq>>5];
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writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET);
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}
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void tegra_legacy_mask_irq(unsigned int irq)
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{
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void __iomem *base;
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pr_debug("%s: %d\n", __func__, irq);
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irq -= 32;
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base = ictlr_reg_base[irq>>5];
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writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR);
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}
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void tegra_legacy_force_irq_set(unsigned int irq)
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{
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void __iomem *base;
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pr_debug("%s: %d\n", __func__, irq);
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irq -= 32;
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base = ictlr_reg_base[irq>>5];
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writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET);
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}
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void tegra_legacy_force_irq_clr(unsigned int irq)
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{
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void __iomem *base;
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pr_debug("%s: %d\n", __func__, irq);
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irq -= 32;
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base = ictlr_reg_base[irq>>5];
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writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR);
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}
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int tegra_legacy_force_irq_status(unsigned int irq)
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{
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void __iomem *base;
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pr_debug("%s: %d\n", __func__, irq);
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irq -= 32;
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base = ictlr_reg_base[irq>>5];
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return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31)));
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}
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void tegra_legacy_select_fiq(unsigned int irq, bool fiq)
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{
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void __iomem *base;
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pr_debug("%s: %d\n", __func__, irq);
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irq -= 32;
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base = ictlr_reg_base[irq>>5];
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writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS);
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}
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unsigned long tegra_legacy_vfiq(int nr)
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{
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void __iomem *base;
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base = ictlr_reg_base[nr];
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return readl(base + ICTLR_CPU_IEP_VFIQ);
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}
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unsigned long tegra_legacy_class(int nr)
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{
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void __iomem *base;
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base = ictlr_reg_base[nr];
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return readl(base + ICTLR_CPU_IEP_CLASS);
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}
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