6865f0ea6a
This adds more full-featured support for the SH7722 Solution Engine. Previously this was using the generic board, and lacked most of the peripheral support. Signed-off-by: Ryusuke Sakato <sakato.ryusuke@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
119 lines
3.7 KiB
C
119 lines
3.7 KiB
C
#ifndef __ASM_SH_SE7722_H
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#define __ASM_SH_SE7722_H
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/*
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* linux/include/asm-sh/se7722.h
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*
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* Hitachi UL SolutionEngine 7722 Support.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <asm/addrspace.h>
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/* Box specific addresses. */
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#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
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#define PA_ROM 0xa0000000 /* EPROM */
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#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
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#define PA_FROM 0xa1000000 /* Flash-ROM */
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#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
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#define PA_EXT1 0xa4000000
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#define PA_EXT1_SIZE 0x04000000
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#define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
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#define PA_SDRAM_SIZE 0x04000000
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#define PA_EXT4 0xb0000000
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#define PA_EXT4_SIZE 0x04000000
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#define PA_PERIPHERAL 0xB0000000
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#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
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#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */
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#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */
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#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */
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#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */
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#define MRSHPC_OPTION (PA_MRSHPC + 6)
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#define MRSHPC_CSR (PA_MRSHPC + 8)
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#define MRSHPC_ISR (PA_MRSHPC + 10)
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#define MRSHPC_ICR (PA_MRSHPC + 12)
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#define MRSHPC_CPWCR (PA_MRSHPC + 14)
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#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
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#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
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#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
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#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
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#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
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#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
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#define MRSHPC_CDCR (PA_MRSHPC + 28)
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#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
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#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */
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#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
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#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */
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/* GPIO */
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#define MSTPCR0 0xA4150030UL
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#define MSTPCR1 0xA4150034UL
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#define MSTPCR2 0xA4150038UL
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#define FPGA_IN 0xb1840000UL
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#define FPGA_OUT 0xb1840004UL
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#define PORT_PECR 0xA4050108UL
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#define PORT_PJCR 0xA4050110UL
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#define PORT_PSELD 0xA4050154UL
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#define PORT_PSELB 0xA4050150UL
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#define PORT_PSELC 0xA4050152UL
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#define PORT_PKCR 0xA4050112UL
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#define PORT_PHCR 0xA405010EUL
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#define PORT_PLCR 0xA4050114UL
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#define PORT_PMCR 0xA4050116UL
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#define PORT_PRCR 0xA405011CUL
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#define PORT_PXCR 0xA4050148UL
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#define PORT_PSELA 0xA405014EUL
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#define PORT_PYCR 0xA405014AUL
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#define PORT_PZCR 0xA405014CUL
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/* IRQ */
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#define IRQ0_IRQ 32
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#define IRQ1_IRQ 33
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#define INTC_ICR0 0xA4140000UL
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#define INTC_ICR1 0xA414001CUL
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#define INTMSK0 0xa4140044
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#define INTMSKCLR0 0xa4140064
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#define INTC_INTPRI0 0xa4140010
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#define IRQ01_MODE 0xb1800000
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#define IRQ01_STS 0xb1800004
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#define IRQ01_MASK 0xb1800008
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#define EXT_BIT (0x3fc0) /* SH IRQ1 */
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#define MRSHPC_BIT0 (0x0004) /* SH IRQ1 */
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#define MRSHPC_BIT1 (0x0008) /* SH IRQ1 */
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#define MRSHPC_BIT2 (0x0010) /* SH IRQ1 */
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#define MRSHPC_BIT3 (0x0020) /* SH IRQ1 */
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#define SMC_BIT (0x0002) /* SH IRQ0 */
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#define USB_BIT (0x0001) /* SH IRQ0 */
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#define MRSHPC_IRQ3 11
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#define MRSHPC_IRQ2 12
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#define MRSHPC_IRQ1 13
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#define MRSHPC_IRQ0 14
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#define SMC_IRQ 10
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#define EXT_IRQ 5
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#define USB_IRQ 6
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/* arch/sh/boards/se/7722/irq.c */
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void init_se7722_IRQ(void);
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int se7722_irq_demux(int);
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#define __IO_PREFIX se7722
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#include <asm/io_generic.h>
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#endif /* __ASM_SH_SE7722_H */
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