fc4effc7a9
A framebuffer driver for the display controller in AMD Geode GX processors (Geode GX533, Geode GX500 etc.). Tested at 640x480, 800x600, 1024x768 and 1280x1024 at 8, 16, and 24 bpp with both CRT and TFT. No accelerated features currently implemented and compression remains disabled. This driver requires that the BIOS (or the SoftVG/Firmbase code in the BIOS) has created an appropriate virtual PCI header. Signed-off-by: David Vrabel <dvrabel@arcom.com> Signed-off-by: Antonino Daplas <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
97 lines
3.2 KiB
C
97 lines
3.2 KiB
C
/*
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* Geode GX display controller
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*
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* Copyright (C) 2006 Arcom Control Systems Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DISPLAY_GX_H__
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#define __DISPLAY_GX_H__
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int gx_frame_buffer_size(void);
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int gx_line_delta(int xres, int bpp);
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extern struct geode_dc_ops gx_dc_ops;
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/* Display controller registers */
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#define DC_UNLOCK 0x00
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# define DC_UNLOCK_CODE 0x00004758
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#define DC_GENERAL_CFG 0x04
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# define DC_GCFG_DFLE 0x00000001
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# define DC_GCFG_CURE 0x00000002
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# define DC_GCFG_ICNE 0x00000004
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# define DC_GCFG_VIDE 0x00000008
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# define DC_GCFG_CMPE 0x00000020
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# define DC_GCFG_DECE 0x00000040
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# define DC_GCFG_VGAE 0x00000080
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# define DC_GCFG_DFHPSL_MASK 0x00000F00
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# define DC_GCFG_DFHPSL_POS 8
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# define DC_GCFG_DFHPEL_MASK 0x0000F000
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# define DC_GCFG_DFHPEL_POS 12
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# define DC_GCFG_STFM 0x00010000
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# define DC_GCFG_FDTY 0x00020000
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# define DC_GCFG_VGAFT 0x00040000
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# define DC_GCFG_VDSE 0x00080000
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# define DC_GCFG_YUVM 0x00100000
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# define DC_GCFG_VFSL 0x00800000
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# define DC_GCFG_SIGE 0x01000000
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# define DC_GCFG_SGRE 0x02000000
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# define DC_GCFG_SGFR 0x04000000
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# define DC_GCFG_CRC_MODE 0x08000000
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# define DC_GCFG_DIAG 0x10000000
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# define DC_GCFG_CFRW 0x20000000
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#define DC_DISPLAY_CFG 0x08
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# define DC_DCFG_TGEN 0x00000001
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# define DC_DCFG_GDEN 0x00000008
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# define DC_DCFG_VDEN 0x00000010
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# define DC_DCFG_TRUP 0x00000040
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# define DC_DCFG_DISP_MODE_MASK 0x00000300
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# define DC_DCFG_DISP_MODE_8BPP 0x00000000
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# define DC_DCFG_DISP_MODE_16BPP 0x00000100
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# define DC_DCFG_DISP_MODE_24BPP 0x00000200
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# define DC_DCFG_16BPP_MODE_MASK 0x00000c00
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# define DC_DCFG_16BPP_MODE_565 0x00000000
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# define DC_DCFG_16BPP_MODE_555 0x00000100
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# define DC_DCFG_16BPP_MODE_444 0x00000200
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# define DC_DCFG_DCEN 0x00080000
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# define DC_DCFG_PALB 0x02000000
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# define DC_DCFG_FRLK 0x04000000
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# define DC_DCFG_VISL 0x08000000
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# define DC_DCFG_FRSL 0x20000000
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# define DC_DCFG_A18M 0x40000000
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# define DC_DCFG_A20M 0x80000000
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#define DC_FB_ST_OFFSET 0x10
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#define DC_LINE_SIZE 0x30
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# define DC_LINE_SIZE_FB_LINE_SIZE_MASK 0x000007ff
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# define DC_LINE_SIZE_FB_LINE_SIZE_POS 0
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# define DC_LINE_SIZE_CB_LINE_SIZE_MASK 0x007f0000
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# define DC_LINE_SIZE_CB_LINE_SIZE_POS 16
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# define DC_LINE_SIZE_VID_LINE_SIZE_MASK 0xff000000
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# define DC_LINE_SIZE_VID_LINE_SIZE_POS 24
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#define DC_GFX_PITCH 0x34
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# define DC_GFX_PITCH_FB_PITCH_MASK 0x0000ffff
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# define DC_GFX_PITCH_FB_PITCH_POS 0
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# define DC_GFX_PITCH_CB_PITCH_MASK 0xffff0000
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# define DC_GFX_PITCH_CB_PITCH_POS 16
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#define DC_H_ACTIVE_TIMING 0x40
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#define DC_H_BLANK_TIMING 0x44
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#define DC_H_SYNC_TIMING 0x48
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#define DC_V_ACTIVE_TIMING 0x50
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#define DC_V_BLANK_TIMING 0x54
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#define DC_V_SYNC_TIMING 0x58
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#define DC_PAL_ADDRESS 0x70
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#define DC_PAL_DATA 0x74
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#endif /* !__DISPLAY_GX1_H__ */
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