Daniel Vetter c2e0eb1670 drm/i915: fix corruptions on i8xx due to relaxed fencing ... It looks like gen2 has a peculiar interleaved 2-row inter-tile layout. Probably inherited from i81x which had 2kb tiles (which naturally fit an even-number-of-tile-rows scheme to fit onto 4kb pages). There is no other mention of this in any docs (also not in the Intel internal documention according to Chris Wilson). Problem manifests itself in corruptions in the second half of the last tile row (if the bo has an odd number of tiles). Which can only happen with relaxed tiling (introduced in a00b10c360). So reject set_tiling calls that don't satisfy this constrain to prevent broken userspace from causing havoc. While at it, also check the size for newer chipsets. LKML: https://lkml.org/lkml/2011/2/19/5 Reported-by: Indan Zupancic <indan@nul.nu> Tested-by: Indan Zupancic <indan@nul.nu> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>		2011-02-24 00:33:49 +00:00
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drm	drm/i915: fix corruptions on i8xx due to relaxed fencing	2011-02-24 00:33:49 +00:00
stub	gpu/stub: fix acpi_video build error, fix stub kconfig dependencies	2011-02-04 12:48:18 +10:00
vga	Merge remote branch 'linus/master' into drm-intel-fixes	2011-01-24 18:27:32 +00:00
Makefile	gpu: Add Intel GMA500(Poulsbo) Stub Driver	2010-10-26 11:00:13 +10:00