32b4f1a4f0
Similar to commit 7d91999954
("pwm: jz4740: Use
regmap_{set,clear}_bits") convert two more regmap_update_bits() calls to
regmap_{set,clear}_bits() which were missed back then.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20240606164047.534741-5-u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
282 lines
7.2 KiB
C
282 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 platform PWM support
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*
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* Limitations:
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* - The .apply callback doesn't complete the currently running period before
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* reconfiguring the hardware.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/mfd/ingenic-tcu.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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struct soc_info {
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unsigned int num_pwms;
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};
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struct jz4740_pwm_chip {
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struct regmap *map;
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struct clk *clk[];
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};
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static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
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{
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return pwmchip_get_drvdata(chip);
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}
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static bool jz4740_pwm_can_use_chn(struct pwm_chip *chip, unsigned int channel)
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{
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/* Enable all TCU channels for PWM use by default except channels 0/1 */
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u32 pwm_channels_mask = GENMASK(chip->npwm - 1, 2);
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device_property_read_u32(pwmchip_parent(chip)->parent,
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"ingenic,pwm-channels-mask",
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&pwm_channels_mask);
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return !!(pwm_channels_mask & BIT(channel));
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}
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static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct jz4740_pwm_chip *jz = to_jz4740(chip);
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struct clk *clk;
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char name[16];
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int err;
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if (!jz4740_pwm_can_use_chn(chip, pwm->hwpwm))
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return -EBUSY;
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snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
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clk = clk_get(pwmchip_parent(chip), name);
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if (IS_ERR(clk)) {
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dev_err(pwmchip_parent(chip),
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"error %pe: Failed to get clock\n", clk);
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return PTR_ERR(clk);
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}
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err = clk_prepare_enable(clk);
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if (err < 0) {
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clk_put(clk);
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return err;
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}
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jz->clk[pwm->hwpwm] = clk;
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return 0;
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}
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static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct jz4740_pwm_chip *jz = to_jz4740(chip);
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struct clk *clk = jz->clk[pwm->hwpwm];
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clk_disable_unprepare(clk);
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clk_put(clk);
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}
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static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct jz4740_pwm_chip *jz = to_jz4740(chip);
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/* Enable PWM output */
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regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
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/* Start counter */
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regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
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return 0;
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}
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static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct jz4740_pwm_chip *jz = to_jz4740(chip);
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/*
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* Set duty > period. This trick allows the TCU channels in TCU2 mode to
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* properly return to their init level.
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*/
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regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff);
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regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0);
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/*
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* Disable PWM output.
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* In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
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* counter is stopped, while in TCU1 mode the order does not matter.
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*/
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regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
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/* Stop counter */
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regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
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}
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static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct jz4740_pwm_chip *jz = to_jz4740(chip);
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unsigned long long tmp = 0xffffull * NSEC_PER_SEC;
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struct clk *clk = jz->clk[pwm->hwpwm];
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unsigned long period, duty;
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long rate;
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int err;
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/*
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* Limit the clock to a maximum rate that still gives us a period value
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* which fits in 16 bits.
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*/
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do_div(tmp, state->period);
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/*
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* /!\ IMPORTANT NOTE:
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* -------------------
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* This code relies on the fact that clk_round_rate() will always round
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* down, which is not a valid assumption given by the clk API, but only
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* happens to be true with the clk drivers used for Ingenic SoCs.
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*
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* Right now, there is no alternative as the clk API does not have a
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* round-down function (and won't have one for a while), but if it ever
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* comes to light, a round-down function should be used instead.
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*/
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rate = clk_round_rate(clk, tmp);
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if (rate < 0) {
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dev_err(pwmchip_parent(chip), "Unable to round rate: %ld\n", rate);
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return rate;
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}
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/* Calculate period value */
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tmp = (unsigned long long)rate * state->period;
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do_div(tmp, NSEC_PER_SEC);
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period = tmp;
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/* Calculate duty value */
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tmp = (unsigned long long)rate * state->duty_cycle;
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do_div(tmp, NSEC_PER_SEC);
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duty = tmp;
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if (duty >= period)
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duty = period - 1;
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jz4740_pwm_disable(chip, pwm);
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err = clk_set_rate(clk, rate);
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if (err) {
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dev_err(pwmchip_parent(chip), "Unable to set rate: %d\n", err);
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return err;
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}
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/* Reset counter to 0 */
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regmap_write(jz->map, TCU_REG_TCNTc(pwm->hwpwm), 0);
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/* Set duty */
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regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), duty);
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/* Set period */
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regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), period);
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/* Set abrupt shutdown */
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regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
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TCU_TCSR_PWM_SD);
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/*
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* Set polarity.
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*
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* The PWM starts in inactive state until the internal timer reaches the
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* duty value, then becomes active until the timer reaches the period
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* value. In theory, we should then use (period - duty) as the real duty
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* value, as a high duty value would otherwise result in the PWM pin
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* being inactive most of the time.
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*
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* Here, we don't do that, and instead invert the polarity of the PWM
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* when it is active. This trick makes the PWM start with its active
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* state instead of its inactive state.
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*/
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if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled)
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regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
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TCU_TCSR_PWM_INITL_HIGH);
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else
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regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
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TCU_TCSR_PWM_INITL_HIGH);
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if (state->enabled)
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jz4740_pwm_enable(chip, pwm);
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return 0;
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}
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static const struct pwm_ops jz4740_pwm_ops = {
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.request = jz4740_pwm_request,
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.free = jz4740_pwm_free,
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.apply = jz4740_pwm_apply,
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};
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static int jz4740_pwm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct pwm_chip *chip;
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struct jz4740_pwm_chip *jz;
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const struct soc_info *info;
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info = device_get_match_data(dev);
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if (!info)
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return -EINVAL;
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chip = devm_pwmchip_alloc(dev, info->num_pwms, struct_size(jz, clk, info->num_pwms));
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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jz = to_jz4740(chip);
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jz->map = device_node_to_regmap(dev->parent->of_node);
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if (IS_ERR(jz->map)) {
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dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz->map));
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return PTR_ERR(jz->map);
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}
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chip->ops = &jz4740_pwm_ops;
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return devm_pwmchip_add(dev, chip);
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}
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static const struct soc_info jz4740_soc_info = {
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.num_pwms = 8,
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};
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static const struct soc_info jz4725b_soc_info = {
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.num_pwms = 6,
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};
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static const struct soc_info x1000_soc_info = {
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.num_pwms = 5,
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};
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static const struct of_device_id jz4740_pwm_dt_ids[] = {
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{ .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
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{ .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
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{ .compatible = "ingenic,x1000-pwm", .data = &x1000_soc_info },
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{},
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};
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MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
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static struct platform_driver jz4740_pwm_driver = {
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.driver = {
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.name = "jz4740-pwm",
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.of_match_table = jz4740_pwm_dt_ids,
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},
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.probe = jz4740_pwm_probe,
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};
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module_platform_driver(jz4740_pwm_driver);
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MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
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MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
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MODULE_ALIAS("platform:jz4740-pwm");
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MODULE_LICENSE("GPL");
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